This lab was really annoying in terms of things that didn’t want to work When trying to export hardware for SDK in PlanAhead error shows [Common 17-49] Internal Data Exception: xps application failed SDK requires gmake, we can solve it by simple linking: cd /usr/bin sudo ln -s make gmake Read more
As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I Read more
In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor. Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. Read more
This week wasn’t the brightest. Our tasks from last week has been dragged to this one which is designing a GPIO and a wishbone interface and a dummy master to drive the GPIO, the later being my task. It was a cloudy day full of rain and sweat, definitely not Read more
In my third week, I worked on designing a GPIO device that uses the wishbone protocol. This project was the same one i was working on last week. I was able to finish my part this week. My gpio basically consists of a direction register and a data register that Read more
This week hasn’t been the most productive for me. I struggled to finish a simple dummy master to test the GPIO and to successfully connect my interface with the GPIO and make sure that all transactions are wishbone compatible. Having examined my results, my supervisor pointed out the following fatal Read more
For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices. While learning what I need to do my new task I Read more
For my second week at AESTE, I was assigned to design and implement a GPIO using the wishbone protocol. The wishbone protocol is a standard method that is used by many processors to communicate to their IO devices. It is a format that uses several several signals in its BUS Read more