Week 0001

Hi, my name is Radek and I am the new intern in Aeste Works. The first week has passed during which I was familiarizing myself with the workplace and the task I will be working on over my 3-months-long internship. My job will focus on describing hardware using a strange Read more

A stumble along the road

This week hasn’t been the most productive for me. I struggled to finish a simple dummy master to test the GPIO and to successfully connect my interface with the GPIO and make sure that all transactions are wishbone compatible. Having examined my results, my supervisor pointed out the following fatal Read more

Second Week: Wishbone SOC

For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices. While learning what I need to do my new task I Read more

First week

My First day started with introducing the workplace and the project I’ll be working on followed by a quick introduction about Verilog and the necessary tools that I need to use to do my work. For this week the goal will be to wrap up all the learning that I Read more

WEEK 3 : ETHERNET

I managed to set up physical layer for ethernet connection after solving the error which came from the .c  file that end with ‘#endif’. I just needed to add an empty line after ‘#endif’ and that solved the problem. When the board was powered up, the LED D8 was blinking, Read more

Week 2 : UART & TCPIP Stack

In order to allow communication between PIC microcontroller and PC, UART communication needs to be set up.  I wrote a program to send data byte from PIC microcontroller to PC which the output was displayed through Minicom, a hyper terminal for linux. At first, the displayed output was gibberish. This Read more