In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor.
Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. The edge detector was used along with several logic gates to indicate the sampling and shifting of bits according to the mode that is given. The edge detector enables the spi slave to function on any clock that is at least twice as fast as the sclk.
Secondly, I combined the read and write registers so that when the data has been transmitted there is a parallel exchange that occurs between the data register and the transmission register. This assures that the circuit design is simple and easier to debug.
I have finished writing my code for the spi slave and am going to work on the test bench.