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Week Six

This is week six of my internship at Aeste Works. After configuring the company’s board to enumerate successfully on a Windows environment, it was time to configure it on Linux. On Windows, the usb drivers loads according to the Vendor ID and Product ID which was for Microchip’s USB CDC Read more…

Connecting Wishbone switches

I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. Read more…

A tale of a Wishbone switch

I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals Read more…

Week Five

This is week five of my internship at Aeste Works. To move forward to what I have to do to implement USB CDC ECM class for ethernet over usb, I’d have to first migrate the USB CDC ACM demo from the PIC32MX which I had been working on last week Read more…

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A Year in Aeste

I’ve finally implemented the base functionalities of the project, and tested that everything works as expected. The only thing that I have left hanging in the dark is finding out how to get the automatic installation of client certificates into browser working. Nevertheless, the application is almost ready to be Read more…

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Week Four

This is my fourth week as an Intern at Aeste Works. My main target this week was to configure the PIC32MX microcontroller as a Universal Serial Bus Communications Class Device that utilizes the Ethernet Networking Control Model (ECM) in allowing the exchange of Ethernet-framed data between device and host. The first Read more…

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One step closer

Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important Read more…

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Week Three

This is week three of my internship at Aeste Works. Three main tasks were assigned to me this week. First was to study on the programming & configuration protocols of three different FPGA’s namely Xilinx’s Spartan-6, Intel’s Cyclone and Lattice’s iCE40. Currently, the company’s own board incorporates the Xilinx Spartan Read more…