Approaching the Finish Line

I am getting close to finishing my part of the project, and only have a week and a half left for this internship period. This week, I have completed integrating the K3rangka with S3padu from the synthesis to bit generation to bram data replacement, writing a function similar to icebram Read more…

Productive Week

This week’s work was very productive in the way that I was able to complete the design flow from synthesis to bitstream generation (excluding bram content replacement) for all 6 fpga types: Xilinx 7 series, Cyclone V, Cyclone IV, Lattice ECP5, Lattice ICE40, and Spartan 6 (which implements the ISE Read more…

Good Progress

At the end of this week, I was able to speak with my supervisor to discuss my progress, mistakes, and next steps. During this discussion, we talked about the importance of representing a product in an understandable and simple manner in engineering, and I thought this was noteworthy. As this Read more…

Changing the K3 Code

This week’s work was focused on writing the code to operate the design flow tools for the Xilinx 7 series, Intel Cyclone V, and Lattice ECP5. I had to gather all the tools I have found during the first few weeks of internship and integrated it into the K3rangka code. Read more…

Starting to Code

I have finally begun making changes to the K3rangka code, trying to isolate the implementations of running yosys, nextpnr, and other tools into separate classes. Previously, the implementation was within the resource file that handles the HTTP requests. The implementation handled different type of FPGAs through if statements, which was Read more…

Almost There

My search for the tools in Vivado and Quartus has come to an end. After three days of unsuccessful attempts to track down the processes while running Vivado and find the tools for each part of the design flow, I have given up and decided to resort to tcl commands Read more…

Searching for the Right Tools

This week, I was focused on finding tools for FPGA boards besides the Ice40 (Lattice ECP5, Xilinx Series 7, and Intel Cyclone V). My starting point was my supervisor’s suggestion to look at project Trellis, X-Ray, and Mistral for each of the boards respectively. Out of the three projects, project Read more…

Photo by Tim Gouw on Unsplash

Getting Started

During my second week of internship, I encountered two unexpected surprises concerned with the project I was given. My project was the continuation of what another intern, Jun Wen, was working on. It was the development of a web application that would simplify the programming of different models of FPGAs. Read more…

Photo by Fabian Grohs on Unsplash

Final Week

This will be my last week of internship in Aeste. I finished up my work on code refactoring. As this will be the last blog entry from me, I would like to write on the learnings and reflections throughout this internship.  I have obtained various technical skills, namely  Git version Read more…

multipart/form-data

I mainly focused on generating a multipart message this week. I was using curl to send a multipart formpost previously. For example, curl -kv -F ‘lang=vlog’ -F ‘[email protected]’ http://127.0.0.4:8080/api/v19/workspace.elaborate was used to transfer data to a server. The request body was shown below. (Note: A boundary was a string of Read more…