Photo by Charles Deluvio 🇵🇭🇨🇦 on Unsplash

Third Week Updates

For the third week, I start with familiarizing myself with carrying out create, read, update and delete operations on the CouchDB database. This involves sending HTTP requests using the Poco library. I learnt to use the “If-Match” header to retrieve a document’s revision so that I can perform update operations Read more…

Photo by Charles Deluvio 🇵🇭🇨🇦 on Unsplash

Continuing with Poco

During the second week, I worked on my assigned project and also received kind guidance from Dr Shawn whenever I’m stuck. My project involves processing final scores of participants in a competition. This calls for pulling data from a CouchDB database after all the marks by judges are dialed in, Read more…

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First Steps

At the start of the internship, I studied Git more in-depth. I appreciate that it will be a valuable tool later on for my projects, such as providing a means of version control. I was given clear briefing about my projects early on by Dr Shawn. My project involves a Read more…

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Warming Up

For my second week of internship I started off by completing the design of the PouchDB Database Schema and finalizing its documentation. With some supervision and minor tweaks, I was able to finish up this task at the start of the week. My internship project for these upcoming several weeks Read more…

Preserving LVM Cache

While there are a lot of examples that describe how to set up a LVM cache on an SSD for a HDD backed storage, they mostly fail to describe an additional step needed to preserve the cache across a reboot on a Ubuntu system. The culprit is that the drivers Read more…

Approaching the Finish Line

I am getting close to finishing my part of the project, and only have a week and a half left for this internship period. This week, I have completed integrating the K3rangka with S3padu from the synthesis to bit generation to bram data replacement, writing a function similar to icebram Read more…

Productive Week

This week’s work was very productive in the way that I was able to complete the design flow from synthesis to bitstream generation (excluding bram content replacement) for all 6 fpga types: Xilinx 7 series, Cyclone V, Cyclone IV, Lattice ECP5, Lattice ICE40, and Spartan 6 (which implements the ISE Read more…