Photo by Giorgio Tomassetti on Unsplash

First Steps

At the start of the internship, I studied Git more in-depth. I appreciate that it will be a valuable tool later on for my projects, such as providing a means of version control. I was given clear briefing about my projects early on by Dr Shawn. My project involves a Read more…

Photo by Vojtech Bruzek on Unsplash

Warming Up

For my second week of internship I started off by completing the design of the PouchDB Database Schema and finalizing its documentation. With some supervision and minor tweaks, I was able to finish up this task at the start of the week. My internship project for these upcoming several weeks Read more…

Preserving LVM Cache

While there are a lot of examples that describe how to set up a LVM cache on an SSD for a HDD backed storage, they mostly fail to describe an additional step needed to preserve the cache across a reboot on a Ubuntu system. The culprit is that the drivers Read more…

Approaching the Finish Line

I am getting close to finishing my part of the project, and only have a week and a half left for this internship period. This week, I have completed integrating the K3rangka with S3padu from the synthesis to bit generation to bram data replacement, writing a function similar to icebram Read more…

Productive Week

This week’s work was very productive in the way that I was able to complete the design flow from synthesis to bitstream generation (excluding bram content replacement) for all 6 fpga types: Xilinx 7 series, Cyclone V, Cyclone IV, Lattice ECP5, Lattice ICE40, and Spartan 6 (which implements the ISE Read more…

Good Progress

At the end of this week, I was able to speak with my supervisor to discuss my progress, mistakes, and next steps. During this discussion, we talked about the importance of representing a product in an understandable and simple manner in engineering, and I thought this was noteworthy. As this Read more…

Changing the K3 Code

This week’s work was focused on writing the code to operate the design flow tools for the Xilinx 7 series, Intel Cyclone V, and Lattice ECP5. I had to gather all the tools I have found during the first few weeks of internship and integrated it into the K3rangka code. Read more…

Starting to Code

I have finally begun making changes to the K3rangka code, trying to isolate the implementations of running yosys, nextpnr, and other tools into separate classes. Previously, the implementation was within the resource file that handles the HTTP requests. The implementation handled different type of FPGAs through if statements, which was Read more…

Almost There

My search for the tools in Vivado and Quartus has come to an end. After three days of unsuccessful attempts to track down the processes while running Vivado and find the tools for each part of the design flow, I have given up and decided to resort to tcl commands Read more…