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Week Ten

This is the tenth week of being an intern at Aeste Works. Continuing from last week,  I found a way to separate normal USB packets and networking packets. This can be done by checking the twelfth and thirteenth byte of the payload found in the readBuffer. Protocols such as IPv4, Read more…

A little bit of everything

This was rather a short week because of the Chinese New Year. Nonetheless, this week I was focusing on modifying AUTO_TEMPLATE for all different modules to generate a top level design. To start off, I was studying the CPU32 module taken from one of the projects and created an AUTO_TEMPLATE Read more…

Generating a single Verilog file

I was working on Icarus Verilog and Emacs in this week. First of all, I would like to introduce Icarus Verilog. Icarus Verilog was a compiler which compiled Verilog code into executable programs for simulation and synthesis. The conventional supported targets were vvp for simulation and fpga for synthesis. These Read more…

Week Eight

This is my eighth week of being an intern at Aeste Works. This week was about setting up and integrating the lwIP stack with the USB CDC ECM device. The device currently does not run with an operating system and so must be configured for the lwIP NOSYS mode using the raw Read more…

Creating a Wishbone RAM

Time was passing really fast and this was the eighth week of internship. In this week I was working on a Wishbone RAM. To start off, I had to understand the mechanism of a dual port RAM. The dual port RAM fundamentally consisted of an instruction port (read only) and Read more…

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A triangular timing diagram

In this week I was modifying the Wishbone switch so that it would gave correct signal outputs. To give an overview, the strobe signal from the previous wire must be passed to the next wire after one clock cycle, until it reached the I/O port. As a result, the I/O Read more…

Week Seven

This is my seventh week as an intern at Aeste Works. This week was about figuring out which part of my USB CDC ECM code interfaces between the host and device in sending and receiving network packets so that I could integrate the lwIP TCP/IP stack later on. There are Read more…

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Week Six

This is week six of my internship at Aeste Works. After configuring the company’s board to enumerate successfully on a Windows environment, it was time to configure it on Linux. On Windows, the usb drivers loads according to the Vendor ID and Product ID which was for Microchip’s USB CDC Read more…

Connecting Wishbone switches

I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. Read more…

A tale of a Wishbone switch

I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals Read more…