My first week at AESTE, I was introduced to something that I have never used before which was the new operating system of Ubuntu. Being a complete tyro at it, I was a little puzzled at how this operating system works. I was required to learn about the GIT software which was very useful in the management of source files. Thankfully, a link to the tutorial was given and it greatly helped me in familiarising myself with the new OS. Read more…
This lab was really annoying in terms of things that didn’t want to work When trying to export hardware for SDK in PlanAhead error shows [Common 17-49] Internal Data Exception: xps application failed SDK requires gmake, we can solve it by simple linking: cd /usr/bin sudo ln -s make gmake After adding Board Support Package in SDK, it is automatically build. While compiling, error shows /bin/sh: 1: arm-xilinx-eabi-gcc: not found Reinstalling the package like described on this page http://www.wiki.xilinx.com/Install+Xilinx+Tools helps Read more…
As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I encountered while going through these tutorials http://www.zedboard.org/course/introduction-zynq as well as their solutions. Proposed solutions are not something new, I didn’t came up with them, this series of posts serves only Read more…
After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal number of syllables. Finally, dialogues are not a legit way of communication between modules. Week’s 0010 assignment was to write a wishbone master module that is a part of a Read more…
In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor. Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. The edge detector was used along with several logic gates to indicate the sampling and shifting of bits according to the mode that is given. The edge detector enables the Read more…
Hi, my name is Radek and I am the new intern in Aeste Works. The first week has passed during which I was familiarizing myself with the workplace and the task I will be working on over my 3-months-long internship. My job will focus on describing hardware using a strange language that seems to be called Very Log. The language itself seems very primitive and lacks adjectives, so describing anything with it seems to be pretty difficult task but my Read more…
This week wasn’t the brightest. Our tasks from last week has been dragged to this one which is designing a GPIO and a wishbone interface and a dummy master to drive the GPIO, the later being my task. It was a cloudy day full of rain and sweat, definitely not the best setting to present your results to your supervisor yet we didn’t heed the warnings of mother nature. The climax was the moment when my supervisor realized that in Read more…
In my third week, I worked on designing a GPIO device that uses the wishbone protocol. This project was the same one i was working on last week. I was able to finish my part this week. My gpio basically consists of a direction register and a data register that are connected to a inout wire. I have several inputs that correspond to the wishbone protocol. These are the data_in, data_out, clk_in, sel_i, we_in, cyc_in and stb_in. the data is Read more…
This week hasn’t been the most productive for me. I struggled to finish a simple dummy master to test the GPIO and to successfully connect my interface with the GPIO and make sure that all transactions are wishbone compatible. Having examined my results, my supervisor pointed out the following fatal mistakes: 1- I mixed simulation commands into my verilog devices code. 2- I still think of verilog as software programming and not as Hardware description language. Here is some tips Read more…
For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices. While learning what I need to do my new task I improved my skills in previously explored topics and came across some nice references. I included those references at the bottom of this article. To learn wishbone SOC I referred to Read more…