For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices.

While learning what I need to do my new task I improved my skills in previously explored topics and came across some nice references. I included those references at the bottom of this article.

To learn wishbone SOC I referred to the wishbone latest specification document

Moreover, referring to projects that are compatible with wishbone such as the following was very useful:

This device was the most useful as it’s a wishbone interconnect similar to what I need to do

The device that I have at the moment is a simple switch with one slave and several masters. The selected master is determined from the address supplied to the slave.

The device I am working on now is a dummy master which controls the slave for testing purposes. It’s a finite state machine.

While I am working, I find it very helpful to start with the simplest possible version of what needs to be done and then developing it into the final product bit by bit. Referring to examples is very helpful as well.

Here is the new references that helped me improve my knowledge of Verilog , emacs and verilog mode:



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