I learned the way of testing a specific function in a program which is built with REST API. Basically every function is assigned to be accessed with either one of four commands (GET, POST, PUT, DELETE). By using CURL command, I can access and test the functionality of a particular function. For the last two weeks of my internship, I am going to work on triggering synthesis for the Verilog output. We are sure that the result is correct because Read more
This week, I am mainly working with JavaScript. I added the simulator into the current project I am working on as a widget to test it out. As expected, I got a few errors and warnings in the console. However, the errors and warnings in Mozilla Firefox and Chrome were slightly different. It turns out that the error that has been bugging me for quite some time was just a silly mistake. In a JavaScript file we loaded , the Read more
This week was spent replicating the functionalities of the previous application but this time with modifications to utilise the REST API as a source for data. Currently while coding up the front-end, there were some minor amendments made to the back-end API to make it more easy to interface with the front-end. With regards to overall front-end progress, the emcee, judge and judgings page are done. For the admin page, it appears that the main functionalities of Admin On Rest Read more
Well, this is my first week of internship at Aeste Works. On my very first day, I told Dr Shawn that I’d prefer to handle software projects rather than hardware. As a result, I’m assigned with the web application project that requires to interface with google drive API. Dr Shawn gave me a lot of useful study materials to study in order for me to handle the job. Therefore, I’m expected to fully master C++, witty (the web application framework Read more
I started this week by doing all the things that Dr Shawn asked to me fix from our last meeting. I created new to data and went from one page to another to see the flow and where the thing went wrong. When I opened up one of the page I realized that the data went missing. I managed to solve that problem and when I opened another page the same thing happened so I just fixed it because the Read more
This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be able to complete all the remaining Keyes modules with minor adjustments for each. While I understood that the analog value is obtained by measuring the time for the capacitor to discharge, as different resistance values would result in a different slew rate, I have been trying all week to get an time Read more
This blog post marks the end of my first week in Aeste. In the past week, I’ve learning up Verilog, Git and the Wishbone protocol so that I am able to understand the work on Alya’s project as she has concluded her internship. I spent a couple of days just getting myself familiar with Verilog code, reading examples and how it’s implemented as well as redrawing the logic circuits that correspond to Verilog code. Moreover, I have learnt to use Read more
This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using regex, I can extract the size of instruction memory and data memory from the elf file. Instruction memory is equivalent to ROM and data memory is RAM. For the company’s current choice of fpga (Xilinx Spartan6 LX9), each block of RAM is 18kbit configurable up to Read more
Basically this week was quiet good for me. After such a long time stuck and trying to fix the bug at last I managed to fix it. The main problem is the way the code filter the fields were wrong which eventually made the aliases and propertyName that I used in View file are not working. After finish fixing the filter, I proceed to fix all the pages that related to it. This bug made me realize that I need Read more
I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so that I can explain everything on the project by going through one by one from the basics to the complicated process of designing in Verilog. At first, I started with showing the Verilog mode in Emacs and viewing waveforms in GTKwave after writing a test bench. After that, I demonstrated the use Read more