This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that describes the circuit I drew. Initially, I started to rely on Icarus Verilog Simulator, which turns out that the output waveform is the ideal waveform that I was looking for. After working and tested for several timing signals, I decided to test it on the Xilinx ISE tools to check on my work.

The Synthesis Error

The 2 out of 3 of my Verilog code that had been written actually failed to be synthesized. I think this happens to most beginner Verilog designers, and it was a sad truth to know that my Verilog code actually suck. I traced the error and debugged on the Verilog codes. And eventually I realized that the always @(posedge ___) cannot be used multiple times for the same register, as it will cause the failure during the synthesis. This actually remind me of the moment where I drew the schematic from the Verilog codes previously. They eventually became my reference on writing my Verilog codes.

As reminded by my supervisor previously, I always drew the schematic before I wrote the Verilog codes. Fortunately, after modifying the Verilog codes several times, I was able to generate the exactly same circuit that I drew, using the Xilinx ISE RTL schematic tool. That was really exciting when I actually see the exact same circuit appeared in the screen! I really appreciate that I drew the schematic out previously. Generation of the schematic is always the most difficult part when come to chip design, it is the part where I spend most of my time on. As I practiced more in the generation of signals, I become more familiar with multiplexers, shift register, LFSR and latches.

Below diagram shows the full timing diagrams that should be generated by the FPGA to the CCD sensor, where HD and VD refer to horizontal drive and vertical drive respectively.

Full CCD Timing Signal

The H1 to H4 signals are horizontal clock CCD signals that should be supply into the CCD sensor, to shift each pixel data out of the CCD sensor to the output amplifier. Previously, I was confused with horizontal drive, as if it should be indicating the new pixel data or the new line. After refer to other camera modules, I came to a conclusion that HD is indicating the new line signals, and VD is indicating the new frame signal of the camera. As for the indicator of new pixel signal would just be the clock signal itself with certain cycles of latency, as described in my previous blog before. These signals are extremely important as they are ready to be used for next stage demosaic processing.


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