This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple Verilog design. The Final Task Since the last task is to design a Verilog module, which I have not been doing it Read more…
This week, new task had been given, which is to design a testing circuitry for the new board that arrived! Wiki Documentation Most of the time I spent is to write the wiki of the project that I had been working for months. Surprisingly I found that some of the Read more…
This week has been spent mainly on documentation of the previous work that had been done. Simplify Code Documenting the code is reminding myself on why do I write it in the way at the first place. Some of the code often comes with unused variable and function where they Read more…
This week, I continued with my previous week task, to find the way on how SPI C code actually work with the Verilog module. I stared on the same circuit for hours, but then I still could not find the way to integrate them together. And finally I decide to Read more…
This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers, which are the control register and data register. However, these assumption can actually be verified through the circuitry of the core itself. Read more…
This week continues with the issue that I had opened previously, which is on the issue that some file is not updated before the synthesis starts. This was a mistake made by the previous intern, that the ramSize (BRAM size) that is needed for synthesis is never been specified correctly Read more…
This week the task is very time consuming, because I spent most of the time debugging and reading the logs in the terminal. As I got to know from my colleague Jeunn Hao, that the simulation still does not work 100% of the time. I decided to read the code Read more…
This week, I have been working mainly on the simulator. Things just don’t work when they are combined 😂 😂 , especially when it is a combination of 3 persons code. It is a critical issue that the simulator is not working. Mainly because I did not understand what had been done by Read more…
This week, my task is to create a cache system for the FPGA synthesis and implementation process, and to kill the previous synthesis process. The cache system would be useful if someone replicates or reuse their design. This saves the processing power and time, where the synthesized file would be Read more…
Continued from last week, I finally manage to automate the bitstream generation. Good news that I have also fixed the problem that causes the hanging of the web application. The hanging is mainly caused by the usage of Wt::WApplication::instance()->deferRendering, because freezes the user interface. The doJavaScript() Problem What surprised me this Read more…