This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers, which are the control register and data register. However, these assumption can actually be verified through the circuitry of the core itself.

Analyze the Core

The most direct approach is to draw out the circuitry of the top module that had been inferred. As I drew out the circuitry of the top module, I only focus on the processor pins, switches and the gpio pins. The main part of identify and verify the problem is from the GPIO module, since the control register and data register is controlled by the address writing to the GPIO module. Where the third bit of the address will correspond to control and data register with 0 and 1 respectively. The hardware circuit removed the byte offset, which ensures that address always increment in byte.

To verify the software part, I traced the simulator instructions, on the store and load instructions that had executed. This also enable me to identify the bug in the C++ code, where wrong register are being read and written to.

SPI communication between the PIC and FPGA

After fixed the bug on the GPIO, I continued with the SPI module. I drew out the SPI module to identify how to write the C++ code, but it is not as easy as I thought it would be. As I draw the SPI module out, I found some minor bug in my inference. Later, I try to follow the arduino SPI library, but I still could not figure out how they actually work with the Verilog module.

Also, inferring the SPI module actually makes the JointJS of the application failed to function properly. Where the wire does not indicate signal anymore. As I traced from the simulator, the instructions seems to be running fine, but the JointJS does not. Since the problem exists previously, I tried to discuss with my colleague Jeunn Hao, and hopefully the problem would be able to solve soon.


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