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A triangular timing diagram

In this week I was modifying the Wishbone switch so that it would gave correct signal outputs. To give an overview, the strobe signal from the previous wire must be passed to the next wire after one clock cycle, until it reached the I/O port. As a result, the I/O Read more…

Connecting Wishbone switches

I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. Read more…

A tale of a Wishbone switch

I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals Read more…

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A week with Verilog

In this week, I was mainly dealing with Verilog. Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had Read more…

The Devil is in the details

This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be able to complete all the remaining Keyes modules with minor adjustments for each. While I understood that the analog value is obtained Read more…