Tagged: verilog

The Devil is in the details 0

The Devil is in the details

This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be able to complete all the remaining...

First hands on experience with Verilog 0

First hands on experience with Verilog

This blog post marks the end of my first week in Aeste.  In the past week, I’ve learning up Verilog, Git and the Wishbone protocol so that I am able to understand the work...

The importance of Simplicity 0

The importance of Simplicity

This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using...

The End of A Journey Does Not Matter, It Is the Journey That Matters, In the End 0

The End of A Journey Does Not Matter, It Is the Journey That Matters, In the End

I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so that I can explain everything on...

Design’s Dependency 0

Design’s Dependency

This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing a robust algorithm. Initially, I made...

When Good Enough Isn’t Good Enough 0

When Good Enough Isn’t Good Enough

I continued to work on the large microphone only to find it was not working. It was weird as it has same characteristics as the small microphone and the design worked on the small...

Module by Module 0

Module by Module

I carried on with the task of designing the modules in Verilog. I had chosen to work on the Infrared Transmitter and Infrared Receiver. This was quite exciting as it was my first time...

Flexibility in Naming 0

Flexibility in Naming

This week, I made a documentation about naming convention. I learned the importance of documentation and communication because it ensures a smooth workflow of project and it helps someone in the future to understand...

Half Done 0

Half Done

At the beginning of this week, I realized I had only another month of internship to go which made me feel bad over the fact that I was not done with at least half...

Input Characteristics Determine Debounce Time 0

Input Characteristics Determine Debounce Time

After much reading and some calculations, I learnt that theoretically the ideal bits of the LFSR counter in my design should result in the range of 300 µs to 5 ms debounce time. The...