In this week, I was mainly dealing with Verilog.
Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had experience with Verilog previously and hence I was very familiar with its implementation. In addition, I tested out a simple AND gate, a comparator, a 3-to-8 decoder and a multiplexer. All of them worked properly. It was simple to compile the Verilog code in terminal with the following commands.
iverilog -o counter counter_tb.v counter.v
Moreover, I learned about emacs verilog-mode which could significantly decrease Verilog coding time. To illustrate my point, by commenting /*AUTOINST*/ in a Verilog file, pressing Ctrl+C followed by Ctrl+A would allow verilog-mode to parse the Verilog code and thus would expand the text after /*AUTO*/ comments. Other useful examples were /*AUTOSENSE*/, /*AUTOARG*/, /*AUTOWIRE*/, /*AUTOREG*/, etc. There were also some advanced examples available in the verilog-mode, such as multiple instantiations, and instantiations using LISP, RegExps or parameters.
Verilator was another free Verilog HDL simulator which compiled synthesizable Verilog into C++ codes. Verilator was certainly useful for converting a Verilog code into a C++ code. I used it to test with my previous Verilog files and a simple Verilator testbench was required in order to run the code fully.
The following commands would translate a Verilog to a C++ class, compile and run.
verilator -cc -convert.v
make -C obj_dir -f VConvert.mk VConvert and obj_dir/VConvert
The output would be in obj_dir/ and Verilog top module would become a C++ class.
Furthermore, I took some time to learn Yosys, which was a framework for Verilog RTL synthesis and it could provide synthesis algorithms for different application domains. An example of a synthesis script was demonstrated below.
read_verilog simple.v #read_design
write_ilang #write the design to the console
hierarchy #elaborate design hierarchy
proc; opt; techmap; opt #the high level stuff
show #display the design
write_verilog synth.v #write design netlist to a new Verilog file
write_json synth.json #write design netlist to a new json file
Besides that, I did some testings with nextpnr. Nextpnr was a FPGA place and route tool. Its design database included Cell, Port, Net, Source, Sink and Arc. On the other hand, its architecture database included Bel, Pin, Pip, Wine, Alias and Group. There were also different tactics to implement nextpnr architecture databases, such as flat database, de-duplicated database and tile-based database. Unfortunately, I was not able to implement nextpnr fully. When I tried to import a json file into the GUI, a segmentation fault was displayed in the terminal. I tried using nextpnr-generic and nextpnr-ice40 but both parties gave the same results.
Info: Importing module simple
Segmentation fault (core dumped)
On Saturday, we were out-stationed to perform a security audit. Thus, I did some read up regarding End User Devices Security Principles. It was a unique experience as I learned to check disk encryption, Trusted Platform Module (TPM), white lister, firewall, virtual private network, etc. The process was rather simple and straightforward.
In conclusion, this was a fruitful and hectic week and I believed there would be more to come.