Photo by Alexandre Debiève on Unsplash

Diving right into Synthesis

In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more…

Photo by Alexandre Debiève on Unsplash

A week with Verilog

In this week, I was mainly dealing with Verilog. Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had Read more…