I returned to AESTE as an apprentice. In these four weeks, I would continue to work on my previous project. First and foremost, I was advised by Dr Shawn to create a configuration class so that it would be inherited by different FPGAs and a factory method should be implemented. Read more…
In this week I was revising some design patterns to utilise them into the software development. A design pattern was a general solution and it had a high reusability. First and foremost, CPU32 was designed as a singleton. It was instantiated only once and there was a global access to Read more…
In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more…
In this week, I was mainly dealing with Verilog. Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had Read more…