In this week I was revising some design patterns to utilise them into the software development. A design pattern was a general solution and it had a high reusability.
First and foremost, CPU32 was designed as a singleton. It was instantiated only once and there was a global access to it, as well as “initialisation on first use”. Lazy initialisation was also required, meaning the instantiation of the class was delayed until it was needed. Fundamentally, I had to ensure that there was only one instance of the singleton class and the pattern had to provide global access to the instance to fulfill the implementation of the singleton. To illustrate my point, the CPU32 class could only have one instance, thus singleton was necessary for CPU32.
In addition, a factory method was utilised for configuring the FPGA board. Factory method was a creational design pattern to define an interface for creating an object, and it would allow the subclasses to decide which type of the objects would be created. It provided standardisation and generic behavior for a superclass and hence subclasses from the client would be used to modify the details of creation. To illustrate my point, the user could configure his FPGA device by first adding #include<Xilinx/Spartan_7>, followed by adding Xilinx::Spartan_7<> X0 to indicate that a Spartan-7 was used. A range of FPGA classes could be instantiated, depending on the preference of the user.
On the other hand, I also automated synthesis in s3padu with Yosys. The system would first generate a Yosys synthesis script, script.ys, followed by executing the synthesis script with the command: $Yosys -s script.ys. I implemented Yosys to run synthesis for Xilinx and iCE40 FPGAs and both were working properly. An example of script.ys was shown below.
read_verilog system.v
synth_xilinx -top systemTop -edif xilinx.edif //run synthesis for xilinx
synth_ice40 -top systemTop -blif ice40.blif //run synthesis for ice40
stat // show statistics
As a result, it was apparent that both synthesis would generate different statistics, and the design elements were distinct from one another. An example of statistics of top level for Xilinx was shown below.
Another example of statistics of top level for iCE40 was shown below.
In conclusion, the progression for this week was good. I would keep on working on the design patterns and finalise the code next week.
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