A New Beginning

I returned to AESTE as an apprentice. In these four weeks, I would continue to work on my previous project. First and foremost, I was advised by Dr Shawn to create a configuration class so that it would be inherited by different FPGAs and a factory method should be implemented. Read more…

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Fin.

This week marked the end of my internship and I was really grateful to have Dr Shawn as my supervisor. I would like to summarise my learning experience over this 12 weeks of internship. Git Git was a version control system to note the progress of software development. Instead of Read more…

Software Design Pattern

In this week I was revising some design patterns to utilise them into the software development. A design pattern was a general solution and it had a high reusability. First and foremost, CPU32 was designed as a singleton. It was instantiated only once and there was a global access to Read more…

Connecting Wishbone switches

I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. Read more…

A tale of a Wishbone switch

I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals Read more…

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One step closer

Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important Read more…

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Diving right into Synthesis

In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more…