This week marked the end of my internship and I was really grateful to have Dr Shawn as my supervisor. I would like to summarise my learning experience over this 12 weeks of internship.

Git

Git was a version control system to note the progress of software development. Instead of passing codes using external hard disk (some companies still practiced this method and it was undesirable), Git allowed developers to distribute and analyse codes more easily. I used to have Graphic User Interface to practice Git in university with GitKraken and it was rather fascinating for me to do Git with Linux platform.

Wt, C++ Web Toolkit

A very interesting fact was that the company was developing web application with C++ framework, instead of using the conventional toolkits such as HTML, CSS and Javascript. A huge advantage of using Wt was that developers tended to have some background of C++ programming so it was relatively easier to do web development with Wt. In addition, Wt was designed to save time and be resilient against SQL injection.

Design Patterns

I was given the chance to do design patterns to allow the web app to determine user’s FPGA. As a result, after reading through most of the design patterns on sourcemaking.com, Factory Method was the most suitable pattern to be implemented. For example, Xilinx namespace was designed using Factory Method and there are four type of classes created in Xilinx namespace, namely Spartan_7, Artix_7, Kintex_7 and Virtex_7. The user could simply inform the web app about his FPGA by doing “#include <Xilinx/Spartan_7>” and he could configure the FPGA by doing “Xilinx::Spartan_7<XC7S6> S1″.

Wishbone Specification

My main tasks were to design an I/O switch, a RAM switch and a RAM based on Wishbone Specification. Wishbone System-on-Chip (SoC) Interconnection Architecture was a flexible design methodology for IP cores. It encouraged design reuse by reducing System-on-Chip integration problems, as different I/O devices might have different ports. It also supported different IP core interconnection, such as point-to-point, shared bus, crossbar switch, data flow interconnection. The process of developing these digital systems based on Wishbone Specification was tedious as there were many signals to be considered, as well as integrating various signals with one another. Furthermore, I had to analyse timing diagrams with GTKWave to ensure that the outputs of signals were correct, according to Wishbone. Overall, I spent about a month to complete all the tasks.

Emacs verilog-mode

Emacs verilog-mode was a great tool that saved a lot of my coding time. To quote directly from veripool.org, verilog-mode “provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time”. As long as AUTO_TEMPLATE was provided, the arguments of Verilog modules could be parsed automatically. I spent quite some time to read up on AUTO_TEMPLATE documentation to do multiple instantiations so that the I/O switches could be connected in a cascading fashion. As a result, ten (or even more) I/O switches could be instantiated without the user to manually input the arguments.

Security Audit

In week 2, we were fortunate enough to have the opportunity of performing security audit at some small companies. We had to study End User Devices Security Guidance for Windows beforehand and on the auditing day we had to check for secure boot, disk encryption, malware, firewall, VPN, white lister, cloud integration, etc. It was a very memorable experience to perform audit with my fellow interns.

All in all, this internship experience was great. AESTE definitely put me out of my comfort zone and I had to be a self-independent learner. I was really grateful to work in AESTE.


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