This was rather a short week because of the Chinese New Year. Nonetheless, this week I was focusing on modifying AUTO_TEMPLATE for all different modules to generate a top level design.

To start off, I was studying the CPU32 module taken from one of the projects and created an AUTO_TEMPLATE for it. The CPU32 had to be connected to a ram switch whereas the ram switch will be connected to an I/O switch. There were ten inputs and twenty outputs for the CPU32 module and hence it was tedious to create the AUTO_TEMPLATE.

In addition, I modified AUTO_TEMPLATE for _T3_Gpio, _T3_Mspi, _T3_Uart and _T3_Sspi modules. This was to ensure that they could be connected to the I/O switches correctly as the previous version of the AUTO_TEMPLATE had some errors regarding the bits passed into the address and data ports. To illustrate my point, the least significant bit (LSB) of the address should be passed into these modules.  

As Dr Shawn previously advised me to modify Verilog files to one block per output due to the fact that an output signal could not be driven by two drivers. There would also be an error when the Verilog files were synthesised with Yosys. As a result, the Wishbone switch had be to modified so that it could be synthesised correctly at a later time.

Furthermore, an error was encountered when emacs verilog-mode was used to parse arguments for aeMB2_edk63 modules. To illustrate my point, the arguments for aeMB2_exec, aeMB2_memif and aeMB2_regs were missing after running the emacs verilog-mode command. This led to a compilation error for Icarus Verilog as well. As a result, I had to look into each of the modules to study the cause of the error. Eventually, I discovered that after I removed /*AUTOINPUT*/ and /*AUTOOUTPUT*/ from aeMB2_exec, aeMB2_memif and aeMB2_regs modules, all arguments could be parsed completely in aeMB2_edk63.

Besides that, I read up on Lattice Preference File, which was an user constrained file for Lattice FPGAs, and it would be used for design planning, e.g. pin assignments. Pin planning was important because it would define the FPGA I/O protocols and locations on the device. Without a proper pin planning, the pins on the board would be randomly assigned and hence different undesirable issues might arise. A User Constrained File (.ucf) could be converted into a Lattice Preference File (.lpf) as follows.

This was an example of a UCF file.

NET “sys_clk_i” LOC = J13;

NET “sys_ena_i” LOC = D14;

NET “sys_int_i” LOC = J14;

NET “sys_rst_i” LOC = F5;

The UCF file could be converted into a LPF file as shown below.

LOCATE COMP “sys_clk_i” SITE “J13”;

LOCATE COMP “sys_ena_i” SITE “D14”;

LOCATE COMP “sys_int_i” SITE “J14”;

LOCATE COMP “sys_rst_i” SITE “F5”;

All in all, the generated top level verilog file with about 5000 lines of code could be compiled with Icarus Verilog without having any syntax errors. I would continue to work on Lattice Preference Files next week as well.

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