I returned to AESTE as an apprentice. In these four weeks, I would continue to work on my previous project.
First and foremost, I was advised by Dr Shawn to create a configuration class so that it would be inherited by different FPGAs and a factory method should be implemented. This would then allow the user to modify the type of FPGA used and hence a correct netlist would be generated from synthesis. After much consideration, I created a class called configurationClass and it would be inherited by three other classes, namely xilinx, ice40 and intel. In this case, configureClass was the superclass whereas xilinx, ice40 and intel were considered as subclasses. The superclass included all standard behaviors and it allowed subclasses to have creation details. Factory method was effective because it allowed the design to be customizable. An UML diagram would be shown below.
An older version of Yosys was installed in the working environment and it could only support limited FPGAs. Thus, a newer version of Yosys was downloaded from Github and it was compiled directly from the source code. CLANG, GNU Flex, GNU Bison, GNU Make, TCL, readline, libffi and xdot were required as prerequisites to compile a complete version of Yosys. This latest version of Yosys would be able to perform synthesis for diverse FPGAs, such as achronix, easic, ice40, xilinx, intel, etc. Hence, I managed to test out synthesis for three different FPGAs, namely ice40, xilinx and intel. A simple Yosys script was demonstrated below to run synthesis. Moreover, synth_xilinx, synth_ice40 and synth_intel by default contained a list of commands, including hierarchy, flatten, memory_bram, memory_map, techmap, opt, etc.
read_verilog ../work.d/system.v synth_xilinx -top systemTop // can be synth_xilinx, synth_ice40 or synth_intel write_edif ../work.d/netlist.edif // can be write_edif or write_blif stat
As a result, the following schematics were generated with graphviz. The imported verilog file was a simple D flip-flop. Additionally, design elements would be different for these FPGAs due to the implementation of different libraries.
Schematic for Xilinx FPGA would be as follows.
Schematic for ice40 FPGA would be as follows.
Schematic for Intel FPGA would be as follows.
Furthermore, I was advised by Dr Shawn to implement Remote Procedure Call (RPC) instead of Representational State Transfer (REST) into the project. I did some reading on RPC and it came to my realisation that RPC was about actions whereas REST was about resources. The general rule of thumb for RPC was that the endpoints should contain the name of the operation. A famous RPC example would be Slack’s Web API, which was shown below.
POST /api/conversations.create Content-type: application/json Authorization: Bearer xoxp-xxxxxxxxx-xxxx
All in all, this was just the beginning of apprenticeship and I would expect more to come.