In this week I was experimenting with Yosys.

Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer level (RTL), logical gate and physical gate level description. Its main purpose, however, was to perform behavioral and RTL synthesis.

In addition, there were several FPGAs which could be synthesized by Yosys, such as Lattice iCE40 FPGAs, Xilinx 7-Series FPGAs, and Intel FPGAs (MAX10 and Cyclone IV). Yosys could also take several formats as input such as Verilog, BLIF, JSON and ILANG. On the other hand, it could produce different outputs such as BLIF, EDIF, Verilog, ILANG and JSON. Thus, Yosys was a robust synthesis library.

Within data flow in Yosys, it would first read design data with frontend modules. The high-level HDL frontends could then generate an abstract syntax tree (AST), which was passed to the AST frontend later on. The AST Frontend would thus compile the AST to the RTL Intermediate Language (RTLIL). On the RTLIL, the design data was transformed via passes. Lastly, backends would convert the design in RTLIL back to text. For example, a Verilog Backend could generate a Verilog netlist.

An example of a synthesis script was demonstrated below.

read_verilog simple.v # read verilog file

hierarchy # check design hierarchy

proc; opt; show # translate processes (always blocks)

techmap; opt; show # mapping to internal cell library

dfflibmap -liberty cmos_cells.lib # mapping flip-flops to cmos_cells.lib

abc -liberty mycells.lib; opt; show # mapping logic to cmos_cells.lib

Furthermore, I performed some advanced syntheses for Xilinx and iCE40 FPGAs. The results I obtained from the syntheses were distinct from one another due to implementation of different libraries. To illustrate my point, there were FDRE and LUT2 design elements for Xilinx but the design elements for iCE40 were SB_DFFSR and SB_LUT4 instead. The following commands were used to run the advanced syntheses for Xilinx and iCE40 FPGAs.

read_verilog simple.v

synth_xilinx # running synthesis for Xilinx FPGAs

synth_ice40 # running synthesis for iCE40 FPGAs

Moreover, Dr Shawn advised me to do research on Wishbone bus interface, which was used by AESTE.

Wishbone was a general purpose interface between IP cores and the standard data exchange between IP modules was defined by Wishbone. Wishbone specification mainly used five keywords, which were Rules, Recommendations, Suggestions, Permissions and Observations. The main advantages of Wishbone were its abilities to promote design reuse by reducing system-on-chip (SoC) integration problems and also to improve reliability and portability of the system. Besides that, the four main types of Wishbone interconnection were point-to-point, data flow, shared bus and crossbar switch. The main Wishbone signals consisted of RST_I, CLK_I, ADR_I, ADR_O, DAT_I, DAT_O, WE_I, STB_I, STB_O, ACK_I, ACK_O, CYC_I and CYC_O, and I would mainly be dealing with STB_I, STB_O, ACK_I and ACK_O. I also read through Wishbone classic bus cycles and local bus handshaking protocol to gain a better understanding of Wishbone.

Dr Shawn also briefly explained to me about FPGA design flow.

There were basically five main FPGA development phases, which were design entry, synthesis, implementation, bit-stream generation and simulation. The design entry could be divided into two phases such as defining structure of the design and creating a schematic design. The synthesis would convert HDL files into a netlist, which was a textual description of a circuit consisting of gates. The implementation would determine the physical design layout, and there were translation, mapping, and place-and-route. Bit-steam generation was to transform the file so that it could be interpreted by FPGAs. At the end of the day, simulation would demonstrate performance of the design.

In conclusion, I was satisfied with the progression for this week and I would continue to work hard for the upcoming weeks.


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