Photo by Alexandre Debiève on Unsplash

Diving right into Synthesis

In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more…

Photo by Tim Gouw on Unsplash

Week Two

This was the second week being an Intern at Aeste. At the start of the week, Dr Shawn explained the overview of the main project that I would be handling during this internship. One of the tasks were to eventually interface a few other popular FPGA’s with the PIC microcontroller Read more…

Photo by Alexandre Debiève on Unsplash

A week with Verilog

In this week, I was mainly dealing with Verilog. Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had Read more…

Chapter 1: Running Man

Yeah! I just finished the first week of my internship at AESTE Works. What a great experience so far. On my first day, Dr Shawn had introduced to me about company rules and sent me a few links to study about Git. Git is the most widely used modern version Read more…