Automate Bitstream: Part 2

The task continues with more challenges, where I start to monitor the synthesis flow that had been set previously, starting from the generation of the HDL file to the generation of the bitstream. Apparently, I found that most of the process are messed up, where the synthesis actually takes place before Read more…

Automate Bitstream : Part 1

The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to be programmed into the FPGA. I found that several links are very useful for studying the flow of synthesis and implementation. Nevertheless, Read more…

FPGA and PIC comms

This week started with a mess. I started to confuse about what is my task all about, until my supervisor clarified me about it. Add a SPI module As I mentioned on my previous post, my task is to assign the SPI module into the FPGA, to form the communication bridge Read more…

Project Continuation

After idling from Aeste for a month, I am back to Aeste again. The task now is to continue working on the previous intern project. Since I am working remotely, I have to setup my working environment to be exactly the same in the office. I chose to setup a Read more…

The Final Week in AESTE

This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my previous blog that, to use RAM to delay the signal, when it is extremely large cycle to be delayed with. My supervisor Read more…

Demosaic: Software vs Hardware

This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the software implementation of demosaicing for various demosaic algorithm, and tested them in Darktable software. The darktable software is very convenient because it Read more…

Demosaic Core on Zedboard

Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx PlanAhead tool, and the excitement on implementation of demosaic core on FPGA. 😆 😆 😆 Using Zedboard to Test the Core This is the first Read more…

Shooting Troubles #3

Continue from the previous blogs, this blog focus on debugging the upcoming errors that may be faced on while using the Zedboard. These errors are the bugs from the Xilinx PlanAhead 14.4, 2012 late version, working on Ubuntu 14.4 operating system. XPSGuiSessionLock Error Initially, I was following the Zedboard CTT ISE 14.4 Read more…

Combination Demosaic Algorithms

Finally, this week I finished on the schematic of the whole demosaic core, described it in Verilog, and simulated it using the Icarus Verilog simulator. In the path of implementation, many problems occurs and it was really interesting to tackle them. The Edge of Bilinear Interpolation Bilinear interpolation is a simple Read more…