After idling from Aeste for a month, I am back to Aeste again. The task now is to continue working on the previous intern project. Since I am working remotely, I have to setup my working environment to be exactly the same in the office. I chose to setup a virtual machine for it, for easier setup purpose. The setup of virtual machine does take some time, and surprisingly after all the installations, it could push and pull from the git server successfully!
Debug the Original Project
Things just do not work well, especially on working environment that newly setup. I tried to run the project like what I did in the office, and it just failed somehow. Since I had left out from the project for some time, I have to debug the project again. The Xilinx tools could be problematic especially the license issue, but most of the error can be solved once the license is verified.
I realized the importance of documentation on the code, which would be extremely useful when something does not work properly. A proper documentation can actually save the debugging time, as well as the understanding of the code flow. This actually cost me some time on the searching some functions that I am seeking for. Apparently, I have to read about Sumia’s blog and code, to understand about what she had done there, and how I am going to integrate my task into the current project.
The new task will be setting up the communication between the FPGA and PIC, through SPI.
The study on SPI is pretty interesting, because it could be connected in two ways, which is the traditional multiple SS pins, and the daisy-chained SPI connections. This gave me some general idea on how to connect the SPI.
The task involves some integration with Alex’s work, where I would need to know about the SPI pins on the PCB. For this week, I had finished the instantiation of SPI core based on previous interns work. The next thing that I need to do is to connect the core to the right FPGA pins, and perhaps start writing some C++ library for the modules.