This week is pretty interesting, as I was working on the timing signals for the CCD. In order to perform demosaicing, my supervisor advised me to understand on the operation of the CCD.
The CCD Phase Signal
The CCD sensor will only operate and controlled by the timing signals that are supplied to the pins. I found this link to be useful in understanding the fundamental of CCD, such as the phase shifting of CCD output. Besides, CCD would have many different output modes that would affect its frame rate. The doubling of the CCD output actually doubles the frame rate. However, I found that many datasheet did not specify how are the outputs would be coming out from the CCD sensor. This actually took me some time to finally realize the CCD output order on each output.
A quad output CCD sensor like figure above would get output from the 4 edges of the frame, which it increases the frame rate by 4 times. Each quadrant output is actually getting from their nearest edges. For example, on the top left quadrant, the pixel output of first line is from the left to the middle of the line. Whereby for the bottom right quadrant, the pixel move from the last pixel of last line to the middle of the last line. Followed by the vertical CCD clock timing, the pixel data will shift from top to bottom for the 2 top quadrants, and from bottom to top for the 2 bottom quadrants. All the quadrants would be reading in the same rate if the all the timing signals for all the quadrant are supplied in the same rate. This also mean that the frame rate is fully controlled by the timing signals, where in my case, I would be using the FPGA to generate the timing signals.
The Necessary CCD Timing Signals
As I discover through the datasheets and schematics, I found that only several timing signals are necessary in order to do the demosaicing, which are the line signal, frame signal and the pixel signal. The line signal would be the vertical CCD clock signal, which is one of the several vertical phase signals. Meanwhile, the pixel signal, which is the horizontal CCD clock signal, could be generated by the ADC timing module. Furthermore, the demosaicing would be done using the output from the ADC, and typically there would be some cycles of latency from the ADC output, which is also necessary to be taken into account during the collection of ADC output.
The following diagram shows the necessary signals that would need to be generated by the FPGA, which specify the line (v1t1,v2t) and frame (v1t2) signal. Using these signals, the pixel signal could be generated by the external ADC modules, to be connected into the CCD directly.
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