Synthesis of Verilog

This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that describes the circuit I drew. Initially, I started to rely on Icarus Verilog Simulator, which turns out that the output waveform is Read more…

Clock is Ticking

This week, I spent a while studying more about stringstream and boostsystem in order to be able to work on separating the upload and download feature into independent WResources to ensure that it can be called by other projects when required i.e. comprise of individual entrypoints. I made a step by Read more…