Tagged: CCD

The Final Week in AESTE

This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my previous blog that, to use RAM...

Demosaic: Software vs Hardware

This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the software implementation of demosaicing for various...

Demosaic Core on Zedboard

Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx PlanAhead tool, and the excitement on...

Combination Demosaic Algorithms

Finally, this week I finished on the schematic of the whole demosaic core, described it in Verilog, and simulated it using the Icarus Verilog simulator. In the path of implementation, many problems occurs and...

Boundary Bilinear Interpolation

This week, things are getting clearer, and the work are getting better. I began to realize my previous mistake, that the image processing pipeline core might be driven in different clock speed, compared to...

Correction on Design and Method

Propagation Delay This week, my supervisor had some discussion with me. The first problems was my timing circuits. Previously, I actually made the timing signals by altering the clock edge, controlling the flip flop...

Synthesis of Verilog

This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that describes the circuit I drew. Initially,...

Timing Signals for CCD

This week is pretty interesting, as I was working on the timing signals for the CCD. In order to perform demosaicing, my supervisor advised me to understand on the operation of the CCD. The...