Starting with Eeschema

Resuming from last week, I continued working on the PCB design for our product. Last week I talked about my experience with learning the basics of designing PCB layout. The first half of this week I studied Xilinx’s PCB design guide for the FPGA, while I focused on creating the Read more…

FPGA Baby Steps

In this week, I started taking my first baby steps in the world of FPGA. I spent some times trying to get myself familiarized with the new tools and concepts. In next paragraphs I’ll try to summarize what I have learned so far .. So let us get started ! Read more…

PCB Designer Life

Have you ever been thrown into the middle of ocean, and you don’t even know how to swim? Well, I have lived this experience, both literally and figuratively. This week it was the latter! But let me assure you, it felt exactly the same both times. Therefore, I am writing Read more…

Witty and HTTP Client

By approaching this week we can finally say that we have completed the first half of the internship successfully . According to our university internship program , the second half is dedicated for the student to carry out a specific project that is related to the host company, so here Read more…

My last week

I have finally completed my internship here in AESTE. I have learned so much here, not just about programming but also learning skills, discipline and time management. For my last week I have finish the basic documentation of my code. The project I have been working on for three months Read more…

Editor Enhancement

In this week , I had to stop working in verilog for a while and get back to do some adjustment and modification to the project web interface. Actually it is really a good thing to break the routine and do something different from time to time :D. If you Read more…

Enhancing the Interface

This was relatively a short week, as today is Thursday and Friday is a public holiday. Moreover, yesterday we left the office at noon to have a farewell dinner for one of the interns and we did not return to the office afterwards. Simply put, the objective this week to Read more…

Building Verilog Modules

Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say that I have successfully completed 12 weeks .. 12 weeks that were full of knowledge, stress, hardworking and sometimes …. fun 😀 Read more…

Testing File System

This week I focus my attention on troubleshooting the problem of the application. As I explained in the previous post of the week, there is a few problems in the application and I have found some solution to solve this problems. Decode signal not exposed in Http Client I refereed Read more…

Application Modifications

The functionality of the Inkscape extensions was almost finished last week. Most of the work I’ve done this week was optimization and modification to different parts of the application. Some of these changes were made to the Witty application (in C++) and some were made to the extensions (in Python). Read more…