In our PCB, we have an FPGA, and PIC18 microcontroller. It is our intention to share one oscillator between the two ICs, hence reducing the cost, and sparing the PCB precious area. This post will discuss the problems that might occur, and what configuration we are using.
Problems can occur when sharing a crystal between multiple ICs, where one IC drives the crystal and its circuit. Also, the combined capacitance of the two ICs might affect the frequency of the crystal and/or degrade the signal. However, sharing an oscillator that contains a quartz crystal resonator, IC driver, capacitors and a buffer can be achieved if both ICs (FPGA and microcontroller) are configured to expect the clock as an input and not drive the crystal. In the case of the PIC18 microcontroller, this means setting the oscillator mode to one of the external clock modes, EC or ECPLL.
Many papers also discusses treating the PCB tracks as transmission lines and properly terminating the line with one of the termination techniques, such as series, parallel, Thevenin or AC termination. The conditions to start treating the PCB tracks as transmission lines are when:
- The one-way signal propagation delay of the tracks is more than a fraction (typically, 1/5 or 1/3) of the rise/fall time of the signal (whichever is shorter). (source )
- The trace length is longer than 1/7 of the largest wavelength of the signal. (source )
For the oscillator we are using, the rise/fall time is 8ns. One third is 2.67ns. For a 2 inch microstrip over an Er=4.0 dielectric (in FR4), the delay would be 270ps. Hence, to exceed the 2.67ns limit the track would need to be 9.8inch. The clock track will be much less than this value, hence the first condition is not satisfied. A good rule of thumb is “2inch/nanometer” (source). That means for every 1 nanometer in the rise/fall time, you can have 2 inch of wire without problems. Applying the rule to our case, for 8ns. we can afford a wire with a length of 8×2 = 16inch.
Now let’s discuss the second condition. Our oscillator frequency is 25MHz. Hence, the largest wavelength is for the 25MHz frequency component. The wavelength equals the signal velocity divided by the frequency. Taking the signal velocity in vacuum 3×10^8, and 25MHz, results in wavelength of 12 meters. In FR4 material the speed of light is 1.5×10^8, which results in a wavelength of 6000mm, or 236.22inch. One seventh of that is 33.7inch. Therefore, in all cases, 25MHz is so small for any problems to happen in our small size PCB.
If, for a different PCB, either one of these conditions applies, then a proper termination should be designed, keeping in mind that there are multiple targets for the signal. For more information on how to terminated a signal for shared clock, check source .
Last problem that might occur when sharing crystal is overloading the crystal with too much load capacitance. Overloading the crystal might result in changing the frequency of the clock, or degrading the clock signal. Load capacitance is “the amount of capacitance that the oscillator exhibits when looking into the circuit through the two ends of the resonator”. This capacitance when used in parallel mode are provided by two capacitors connected to the crystal ends. In our case we are using an oscillator than contains the load capacitance as well as a buffer. Hence the effect of the internal capacitance of the two ICs will be minimal. For more information regarding crystals, oscillators and load capacitance check source , the technical support page of the oscillator manufacturer TXC corporation.
In our circuit, we have one oscillator (8W-25.000MBA-T or 8C-25.000MBA-T) and it will be connected to both the FPGA and the microcontroller. From the discussion above, it appears that there are no practical problems in doing that. PCB routing considerations for the oscillator still applies, such as placing the oscillator as close as possible to both ICs.