Resuming from last week, I continued working on the PCB design for our product. Last week I talked about my experience with learning the basics of designing PCB layout. The first half of this week I studied Xilinx’s PCB design guide for the FPGA, while I focused on creating the schematic for the circuit in the other half.

FPGA PCB Design Guide
Spartan-6 FPGA PCB Design and Pin Planning Guide is a detailed document discussing – as the name implies – all aspects with regard to PCB designing of Spartan-6 FPGA. It starts by explaining PCB technology basics and terms, then talks thoroughly about Power Distribution Systems (PDS) where it specifies the required capacitors for each FPGA and explains concepts such as capacitors parasitic inductance and effective frequency. These concepts are important to understand the operation of the decoupling capacitors, determine where should they be located in the PCB, and to be able to substitute them if necessary. The document continues to discuss SelectIO signaling, PCB materials, and Design for high-speed signals. At the end, it highlights a recommended PCB Design rules for QFP, BGA and CSP packages.
Although some concepts and specification discussed are important when creating the schematics, the document focuses mainly on the PCB designing guidelines. Hence, for now, I will not be dealing with most of it concepts, and I will definitely be consulting it later when I finish the schematics and start working on the PCB layout.
Diving into Eeschema

Enough with the theory and PCB guidelines. It is time to start with creating the circuit schematics. KiCAD is a collection of programs, and Eeschema is the one that creates the circuit schematics. When I was looking at other schematics on the Internet, or trying to understand the previous PCB design of our product, I found out that there are many features of Eeschema that I don’t yet know. So, I started exploring and learning.

Creating a multi-part component

The first thing I needed to do with Eeschema is to create a new component for the FPGA. And since the FPGA package we are using contains 256 pin, it is not advised to create one big component with all the pins in it, but rather divide the FPGA into parts and create a multi-part component. This will make connecting and managing the component much easier, and enables dividing the circuit into multiple sheets with each containing a part of the FPGA e.g. power connections of the IC, go to the power sheet, and so on. As you would expect, it is a built-in feature of Eeschema and you can specify the number of parts (up to 26) when creating a new component in the library editor. The only confusion I experienced is that, by default pins are shared across all parts, hence, when modifying or adding a pin in any part, the pin will be created (or modified) in all the other parts. From Eeschema Reference Manual, I found the option to disabled this behaviour, and I got to understand that this option is prefered for most applications!

Next, I needed to understand how KiCAD assigns the pins to their corresponding pads in the PCB footprint, i.e. its location on the physical component. Pins have names and numbers. For most pins (except hidden power pins), KiCAD uses the pin number to assign it to the pad that has the same number. Luckily, KiCAD has the footprint for our FPGA package, BGA256, and its pads uses the same numbers as in here, letters for rows, and numbers for columns. For more information about pins names and numbers and how hidden power pins differs, check this link.

Finally, I created the multi-part component for the FPGA spartan-6 with BGA package.




Hierarchical schematics

For complex projects, more than one sheet is needed to contain the schematics. Sheets can be either “flat” or hierarchical sheets. Both can work, but hierarchical sheets provide more flexibility and features that can facilitate the process of creating the schematics. With hierarchical sheets, the structure of the schematics can be easier to construct, manage and understand. Also, hierarchical labels provide a convenient way to extend signals to other sheets instead of using global labels.

Eeschema Reference Manual contains a detailed explanation of the hierarchical schematics.


Final thoughts

At the end of the week I started to create the connections of the components in the schematics. Well, I did not connect anything yet, but rather read on the process of configuring the FPGA, and using a microcontroller to do that. Also, I started reading on the PIC18 that we will be using and getting to know what connections are needed for it to operate. Next week I will continue down this road, and hopefully I will post some circuits!

Talk to you next time.

P.S: I think I am starting to learn how to swim in this ocean!


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