In this week, I started taking my first baby steps in the world of FPGA. I spent some times trying to get myself familiarized with the new tools and concepts. In next paragraphs I’ll try to summarize what I have learned so far .. So let us get started !
What is FPGA ?
FPGA stands for field programmable array. It is simply a programmable chips that can be programmed to do any digital functions. The general work flow you need to follow when you want to work with FPGA (regardless of its vendor ) is as follows:
First you need to get your logic functions done (Design entry step). You can use schematic or any of the HDL languages (verilog or VHDL) then you simulate, synthesis , map , place and route, and finally implement. The output of this process is simply a binary file that can be downloaded into the FPGA.There are two main vendors of FPGA : Altera and Xilinx.
In our project we will be using Xilinx Spartan-6 FPGA. Each FPGA family has its own specifications so you have to be aware of which one your using and always refer to its Datasheet. Xilinx ISE design suite software is used to program the FPGA. The tools is equipped with others tools to do the synthesis (XST) and Isim for simulation and so on. I found these following pages useful you can follow them to gain better understating 😀 :
First step: Design Entry
Top Level SOC:
So after this brief introduction about FPGA and its work environment. I started getting my hand dirty, the task I was planning to accomplish in this week was to complete a simple soc module (verilog top level module that contains processor, 16 KB RAM and one I/O which is in this case a gpio) and then start playing with the synthesis tools and so on. But unfortunately the first part required much time than I expected.
The processor is AEMB processor (EDK63) that has three wishbone interfaces: one for the data bus, one for fetching the instruction from a memory (in this case the 16 Kbyte RAM) and one for accelerators . Getting to connect the processor through the data bus interface with I/O (GPIO) was straight forwarded task specially in this case where there is only one I/O therefore there is no need for switch or multiplexer (later another 16 kbyte data ram will be needed). It is just a matter of connecting the wishbone signal together. But the task started to get ambiguous as I started working with the processor RAM connection.
As this was my first experience with the FPGA I had no prior knowledge on the internal architecture of the FPGA. I thought it was just a vast vacuous land where you can plant whatever you want but apparently I was wrong as the next paragraph will show you.
In Xilinx FPGA there are two types of internal RAM. One is known as a distributed RAM and the other one is the BLOCK RAM. The distributed RAM is used when small memory needed. It’s implemented using the logic cells ( consumes the chip available resources), on the other hand the BLOCK RAM is located in dedicated area in the FPGA. They can be used when large memory is needed. These blocks can only be used as RAM if you don’t use them you are simply going to loose them. (So as you can see beside the logic cells(the vast land) there is a dedicated area that can not be used for any thing else other than the RAM ).The choice of your memory type is actually based on your memory size requirement. In our case since we need 16 Kbyte memory so we will be stick with the Block RAM or (BRAM). To add the BRAM to your design you can either instantiate or inference. Each method has pros and cons. Please refer to the following link for more info.
In our case we will be using the inference method to add our BRAM to our design. In the inference method you just simply give a description of the logic you want to implement then the XST (Xilinx Synthesis Tool) will take care of the rest.
You can refer to XST tool guidelines the section of HDL coding technique to see how to write an HDL code that can be later interpreted as BRAM.
When I came to write a RAM logic description, the point is that this RAM should be able to communicate with processor through a wishbone interface. It is actually my first time to attempt to write full verilog module that has a wishbone interface .. hmm I’m currently stuck in this point, Hopefully I’ll get it done soon.