In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation of all the modules (processor, switch and some I/O devices ) needed in the top level module and started the connection and wiring between them. If you are following my blog entries you will notice that I have encountered some issues with the switch module as we had two routes to take, either to instantiate one big switch that connects the processor to other I/O devices or small switches that can be cascaded based on the need. As I mentioned before the big switch has the capacitance problem as the number of I/O devices increases the distance between the I/O ports will decrease which will eventually lead to high capacitance in the chip and that may reduce the speed of processing. Therefore we decide to build our top level module using the cascading switches technique. If you remember, last week I managed to get the switches cascaded but there was a problem as the algorithm I created tended to connect the I/O device to the long wire connection (Refer to my previous blog entry for more info ) , in this week I had to fix things up so the I/O devices are always connected to lower layers switches before the upper layers ones.
Finally I can say that I managed to get the algorithms right so the I/o devices are now connected to the lower layer switch first before the next layer switch . That means The lower switches available spaces and address will be filled up first before the upper ones and by this we will make sure that the I/Os have the shortest available wires to the processor.
After getting the connection done, I had to work on extracting the address of I/Os devices. Each switch has a decoder. The decoder will assert the strobe signal of the I/O that the processor wishes to communicate with. It decides which I/O to enable based on certain bits on the address that comes from the processor. Here, I had to revise the concept of address decoding to really understand what information the address contains. Address decoding is the process of generating chip select signals from the address bus for each device in the system. The address can be divided into two sections the N most significant bits are used for the generation of the chip select signals while the M least significant signals are passed to the devices as addresses to the different memory cells or internal registers.
So that means the switch will check the N most significant bits of the address in order to decide which I/O the processor wishes to communicate with.
The picture above is only for illustration purpose.
The algorithm I made to extract the I/O address is quite simple and straight forward and it’s actually based on the method I used for the connection. As you can see in the above picture the first available slots of any switch go first to other switches before the I/O devices. So simply I used the concept of look-up table (an array that holds a set of pre-computed results for a given operation. ) .The look-up table contains all available addresses in the system. The first addresses go to the available switches(1,2,3 ..) and the rest will be assigned to the I/O devices.
In the picture above the I/O device “Io1” will be assigned to the first available address after the switch1 just because it has been declared first by the user in the C++ code. So when we want to fetch its address from the look-up table all we need to do is simply to know its order in the C++ code. By following the same concept we can fetch the address of all devices based on their order of declaration in the user C++ code.
The following table shows the assigning of the available address to the devices in the example above.
Available address device
Thanks for reading and see you next week. 😀