Test bench can be deterministic or self-checking. In deterministic test bench, the design’s output are simulated according to the design’s state and inputs specified in the test bench. A designer would then have to validate that the outputs are working as it should. Meanwhile, in self-checking test bench, expected results Read more…
This week started off with me panicking when I could not find my saved files and codes. I asked Dr. Shawn about it and he fixed it rightaway so I was able to access everything again. Turns out, it was because of a black out which affected our server. Then, Read more…
Dr. Shawn would always remind me not to be consumed or lost in the programming language while learning Verilog as it describes the schematic in designing chips and must be approached as such. Treating it like a normal programming language will not be the right way to study Verilogs. This Read more…
This week I continued to study further on the topic of Wishbone signals and also communication protocols. I tried creating testbenches for available codes that had been designed to observe the waveform output but failed to compile it because there were errors. Dr. Shawn pointed out that it was due Read more…
This week I was assigned a few tasks by Dr. Shawn. The first one is to familiarize myself with tools such as Emacs and GTKwave. Emacs is a handy text editor which are extensible and can also be customized. Meanwhile, GTKwave is a tool for viewing and analyzing waves. I Read more…
This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple Verilog design. The Final Task Since the last task is to design a Verilog module, which I have not been doing it Read more…
This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers, which are the control register and data register. However, these assumption can actually be verified through the circuitry of the core itself. Read more…
The task continues with more challenges, where I start to monitor the synthesis flow that had been set previously, starting from the generation of the HDL file to the generation of the bitstream. Apparently, I found that most of the process are messed up, where the synthesis actually takes place before Read more…
The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to be programmed into the FPGA. I found that several links are very useful for studying the flow of synthesis and implementation. Nevertheless, Read more…
After idling from Aeste for a month, I am back to Aeste again. The task now is to continue working on the previous intern project. Since I am working remotely, I have to setup my working environment to be exactly the same in the office. I chose to setup a Read more…