This week started off with me panicking when I could not find my saved files and codes. I asked Dr. Shawn about it and he fixed it rightaway so I was able to access everything again. Turns out, it was because of a black out which affected our server. Then, I continued practicing the drawing of schematic diagram from reading the Verilog codes. Dr. Shawn helped me in explaining certain part of the codes which I did not understand. It did not help that my basic was not strong as I still could not remember some statements’ function.

I familiarized myself with Xilinx ISE tool for synthesizing and analyzing HDL designs. To improve a design, the analyzation must be made at the design’s speed and size. From there, it should then be converted to available hardware chips with respective to the board desired. I made few changes to the codes to observe the difference. I hope to gain the skill of optimizing the design later. The general project flow of my internship was made clear by Dr. Shawn and I look forward to accomplish more in the months to come. I must improve my work performance since a month of my internship was not productive enough.

I work with two other interns here, Sina and Akel. This was the last week at Aeste for Akel so Dr. Shawn brought us for a lunch and a movie together. It was fun and the movie was great.


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