Engineering Elegance

LLVM: Target Specific Attributes.

In LLVM system compiler, there is an option in the command command -mattr called target specific attributes. You may check each target attributes by using this command. llvm-as < /dev/null || llc -march=aemb -mattr=help note that -march=aemb is to select target architecture, in my case, aeMB. A list of attributes will appear as below. Available features for this target: barrel – Implements barrel shifter. div – Implements hardware divider. efsl – Implements extended FSL instructions. esr – Implements ESR and Read more…

By tedxmmu, ago

uCLinux: Jiffies in the Kernel

Having the discussion of tick rate in my previous post, it is therefore appropriate to introduce jiffies in linux kernel. Jiffies is a global variable declared in <linux/jiffies.h> as: extern unsigned long volatile jiffies; Its only usage is to store the number of ticks occurred since system start-up. On kernel boot-up, jiffies is initialized to a special initial value, and it is incremented by one for each timer interrupt. As discussed in the previous post, since there are HZ ticks occurred in one Read more…

By cyberglory, ago

LLVM: Customize your Instructions.

For the past few weeks, I was given a task by my supervisor. The task sound simple, whenever there NOP (No operation) instruction will be use, LLVM should change it into XOR R0, R0, R0 which basically doing nothing since in aeMB, register zero (R0) always have zero values. NOP –change to–> XOR R0, R0, R0 So I start digging. First I look into *InstrInfo.td because thats where all target specific instructions were define. And the tablegen will automatically generate Read more…

By tedxmmu, ago

uCLinux: Tick Rate

With a large number of kernel functions are time-driven, the time management in kernel is very important. The frequency of the system timer (tick rate) is programmed on system boot based on a static preprocessor define, HZ. The value of HZ is architecture-dependent, and it is defined in: <asm/param.h>. The tick rate has a frequency of HZ hertz and a period of 1/HZ seconds. For example, by default the architecture defines HZ to be 100. Therefore, the timer interrupt on the system has a Read more…

By cyberglory, ago

After life: There is a Need to Improve

I had officially completed my internship life in AESTE. Finishing my internship makes me wonders about my future. This feeling was never so intense. I never worried about my future so much before, when I was in my university. My supervisor told me that engineering is all about efficiency. He showed how naively I had implemented my code, without considering much about readability and capable for other people to handle in the future. These are really inspiring. These does not Read more…

By tanagabiru, ago

Internships at AESTE

Listen to one of the interns here talk a little about his internship experience at AESTE. The work we do is HARD – but fruitful. The working culture here is different – in a good way. You get to meet other interesting people – who will enrich you. An internship at AESTE is guaranteed to push you to discover strange new things about yourself. Read what other interns learned through their experiences here. Apply now!

By Shawn, ago

Z: Doesn’t She Look Good

Anyone who has a hobby would understand the satisfaction of completing something on which he or she enjoyed working. It doesn’t always look marketable, it doesn’t always look fashionable, it doesn’t always look picture-worthy. But it always looks good to the creator. Anyone who has a job would understand that that is never enough. Anything that looks good only to its creator has little value to the rest of the world and is largely irrelevant in the grand scheme of Read more…

By philipzloh, ago

Misunderstood Motivations

In the latest blog entry from one of our AESTE interns, he raised a couple of pertinent questions with regards to the very raison d’etre at AESTE. I thought that this might be an opportune time to address the issue. First, I shall address a very commonly held misconception – “What use is the fastest multi-threaded 32-bits when others have already multi-core 64-bits”. Global Microprocessor Market Most people will probably think along the same lines except people who are in Read more…

By Shawn, ago

Code is never finished.

Towards the second half of my internship, I extended my working hours. I knew that if I don’t, I’ll never be able to achieve anything in the end. Now the day had come that I have officially finished my internship. My code still have a lot of bugs and holes. My triumph had failed me. AESTE is at the level that will not be fully understood by anyone. Many of my course-mates are skeptical on the future of AESTE. Before Read more…

By tanagabiru, ago

ASH1: Architecture

After summarizing USB Operations, time to kick off the ball for the match of ASH vs. IOP The general view of ASH1 processor is as the following: ASH1 is a stack-based processor, where the majoroty of the operations will be done on a stack, this participates in reducing the instructions operands. The initial plan was to make ASH1 a multi-cycle processor but with the introduction of an instruction memory unit, ASH1 is generally a single-cycle processor with the exception for Read more…

By mesopotamiascorpio, ago