For my second week at AESTE, I was assigned to design and implement a GPIO using the wishbone protocol. The wishbone protocol is a standard method that is used by many processors to communicate to their IO devices. It is a format that uses several several signals in its BUS to facilitate the transportation of data to and from IO devices.

I was particularly asked to focus on the IO device that adheres to the protocol. Initially my first approach was to design the GPIO using finite state machines because I thought the protocol contained sequential and combinatorial logic. However I was surprised to find that a GPIO uses only needs two flip-flop registers and a few tristate buffers and muxes to work.

I am still currently working on the design as my last design was faulty in the sense that it didn’t utilize the direction registers to store the address of the input/output. When I finish the design, I will be sure to post it up.


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