Creating a Wishbone RAM (Update March 2019)

Time was passing really fast and this was the eighth week of internship. In this week I was working on a Wishbone RAM. To start off, I had to understand the mechanism of a dual port RAM. The dual port RAM fundamentally consisted of an instruction port (read only) and a read/write port. An address of 0x00000000 would be passed into the instruction port whereas 0x80000000 would be passed into the read/write port. However, they should have the same data Read more…

Reaching a Milestone

So I managed to implement the reusing of private keys as part of the renewal process. The problem was that I was calling the wrong API for Botan, which yields an unexpected outcome. Shortly after that, Dr Shawn wanted me to implement one more feature for the application. It basically involves checking whether the user receives the email for the certificate download or not. This can be done using the Post Office Protocol version 3 (POP3). When we send the Read more…

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A triangular timing diagram

In this week I was modifying the Wishbone switch so that it would gave correct signal outputs. To give an overview, the strobe signal from the previous wire must be passed to the next wire after one clock cycle, until it reached the I/O port. As a result, the I/O would asset an acknowledgement signal, which would negate the current strobe signal. And the acknowledgement signal would be passed to the next wire after one clock cycle as well. This Read more…

Week Seven

This is my seventh week as an intern at Aeste Works. This week was about figuring out which part of my USB CDC ECM code interfaces between the host and device in sending and receiving network packets so that I could integrate the lwIP TCP/IP stack later on. There are two functions that were found in the code that sends and receives data.  First, the application can send data to the Host by using the USB_DEVICE_CDC_Write function.  This function requests Read more…

Week 2 in 2019

Nothing much to be said for this week. I attempted to implement based on what Dr Shawn suggested to me last week, i.e storing the public and private key pairs in the database, so that the private key could be reused for subsequent certificate renewals. This relies on the user having to present the old certificate, which contains the public key that would be used to find the matching private key in the database. If no certificate is given, then Read more…

Week Six

This is week six of my internship at Aeste Works. After configuring the company’s board to enumerate successfully on a Windows environment, it was time to configure it on Linux. On Windows, the usb drivers loads according to the Vendor ID and Product ID which was for Microchip’s USB CDC Abstract Control Model demo. USB CDC Ethernet Control Model is widely used for interoperability with non-Microsoft operating systems, but does not work with Windows and this meant that even with the Read more…

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Connecting Wishbone switches

I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. WE_O: It would be asserted during WRITE cycles and negated during READ cycles. CYC_O: It would be asserted throughout all bus cycles. SLAVE signals SEL_I: It denoted the location of Read more…

Starting the New Year with a Bang

Hello everyone, and happy 2019. I’m back writing the first blog for the new year and to inform my dear readers, whoever it may be, of the status of my project. Hoping back into the project, the only problem that I have to deal with now is getting the automatic installation of client certificates to work. I had run into some major problems regarding this, as I had outlined in a previous blog. Anyways, looking back into it, nothing good Read more…

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A tale of a Wishbone switch

I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals below based on the Wishbone specification. DAT_I: It denoted the data input array, the size of the array was determined by the port size DAT_O: It denoted the data input Read more…

Week Five

This is week five of my internship at Aeste Works. To move forward to what I have to do to implement USB CDC ECM class for ethernet over usb, I’d have to first migrate the USB CDC ACM demo from the PIC32MX which I had been working on last week to the PIC32MZ in which the company’s own board utilises. I was provided a schematic showing the pinouts of the custom board and was tasked to implement a simple LED Read more…