This week, I was focused on finding tools for FPGA boards besides the Ice40 (Lattice ECP5, Xilinx Series 7, and Intel Cyclone V). My starting point was my supervisor’s suggestion to look at project Trellis, X-Ray, and Mistral for each of the boards respectively. Out of the three projects, project Trellis seemed to have the most progress as it was able to support a full design flow from Yosys to nextpnr to bitstream generation using a tool named ‘ecppack’. However, the project did not contain any tools to replace the b-ram contents of the fpga as what the ‘icebram’ tool from project Icestorm did. Project X-Ray did not support a design flow from nextpnr yet (it is said to come) and project Mistral was in a very early stage of development (not even sure if it will support nextpnr).
Therefore, for the Xilinx and Intel boards, I had to resort to the software programs from those companies to find the tools I need. The two programs were Vivado and Quartus. In order to have a better understanding of the overall FPGA design flow and how Vivado works, I spent a day learning how to write a basic Verilog script with a test bench, and use Vivado to simulate and generate a bitstream file. Then, I was suggested by my supervisor to use the Linux terminal in order to track down the processes that run during each of the design flow processes. In one of these processes will be a tool for me to use. This was a tedious task and is yet to be completed. Looking at the files that are involved with these processes, I feel that it is inevitable for me to learn how Linux shell scripts work, which will be my first thing to learn next week.