Chronicles from our peeps.
My internship in Aeste has come to an end. It has been quite a unique experience. I started the internship with some rough scolding and was nearly fired on my first day because I did not finish the pre-internship studying materials. Luckily, I stayed on for another 16 weeks. In Read more
This week, we Aeste interns had much fun where our boss brought us for movie on Wednesday and a farewell lunch for Peter (bye Peter!) on Friday. As for me, this would be the second last blog post. Using Boost::property_tree Back on topic… I mentioned last week that I was Read more
This is my fifteen week in AESTE finishing up my PCB design project. ..-“””””-.. .’ ___ ‘. / .”\ `\ \ ; /, ( | ; ; /_ ‘._ / ; | |- ‘._`) | ; ‘-;-‘ \ ; ; “””” / MY \\ ; \ ‘2 Cents’ / ‘._A Read more
This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my previous blog that, to use RAM to delay the signal, when it is extremely large cycle to be delayed with. My supervisor Read more
This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the software implementation of demosaicing for various demosaic algorithm, and tested them in Darktable software. The darktable software is very convenient because it Read more
This is my fourteen week in AESTE with Schematic done proceeding to PCB design about 50% done. The PCB design is a Four-layer board, signal -ground – power – signal. I am pretty thankful and grateful to be able to do PCB design, the main reason is because to me, Read more
In Aeste, we learn something new every day, except for weekends, because we don’t work on weekends :). Dr. Shawn was here for a few days and it was nice to have his guidance and insights on things. The past weeks I have worked on the project, I kept adding Read more
This week has been a roller-coaster ride for me. There were times when Wt just refused to be a good sport, times when we made great and wonderful progress and also times when I thought Wt wronged me, but turned out I did not understand it enough. As usualy, I Read more
Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx PlanAhead tool, and the excitement on implementation of demosaic core on FPGA. 😆 😆 😆 Using Zedboard to Test the Core This is the first Read more
Continue from the previous blogs, this blog focus on debugging the upcoming errors that may be faced on while using the Zedboard. These errors are the bugs from the Xilinx PlanAhead 14.4, 2012 late version, working on Ubuntu 14.4 operating system. XPSGuiSessionLock Error Initially, I was following the Zedboard CTT ISE 14.4 Read more