This week just goes by so quickly, and it is a week where i do not have a senior intern to help out with my project. My this week challenge is to implement SSL with PIC18F. I’ll be using the TCPIP source code provided by Microchip Technology for my project. Read more…
Hi everyone, aeste works is now occupied by four interns. Our veteran, khai yong (Peter), my colleague + current uni-mate, Alex, maisha who is an EE student in APU and lastly yours faithfully. If anyone is looking for a challenging internship that will test you to your limit, do send Read more…
This week I working on the TCP network performance. I needed to collect the data and make a graph for analyzing purposes. I had collected 15 samples for each RX and TX pin, which buffer size range from 100 to 1900. I have created a large dummy file to test Read more…
There are few results that had been obtained to testing the performance of the RTOS. Compare the relationship between instruction cycle used for initialization with different optimization level in different type of RTOS For initialization OS, FreeRTOS is much more higher than Contiki. The is due to there are a Read more…
Hi everyone, I’ve just started my work as an Intern Engineer in AESTE and today marks the fourth day which I have spent in this company. For the next 15 weeks (if I’m still an intern here), I will fill up this blog with my weekly personal experiences and learning Read more…
Time passes quickly and my internship has come to an end. Throughout this journey I have learnt a lot and gained a lot of new insights especially from my supervisor, Dr Shawn. I would like to extend my appreciation to Dr Shawn for all his guidance and advice in this journey. Read more…
Now that my week 3 has passed, I would say I am not as clueless as before. I have shown my previous week’s work on witty application with backend WResource to Dr Shawn. Subsequently it was followed by a session defining my aims in the project I have been assigned. Read more…
This week, I had been assigned task on learning the schematics from Verilog. Schematic of Xilinx ISE I think this is a good approach in learning Verilog, because I actually get to know how does the Verilog codes affect the circuits. At first, I was merely following the schematics that Read more…
First day of work already got scolded by the Boss, “Another two useless Intern!”, “Call Rodney now,” “I’m thinking whether to fired you 2 now, cause i won’t lose anything”, “simple things also cannot do”, “if you don’t understand read more lah, I give you all so much time and Read more…
Another week has passed in AESTE and although Dr Shawn was not around for the time but there was no lacking in my learning curve. My senior interns (Sumia, KY and Islam) had always tried to pass down the knowledge they have earned throughout. I am more than blessed to Read more…