Wishbone Bus Interface
In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ).
My task for this week was to connect and wire these instance modules together using the WISHBONE bus interface. The first question came to my mind was “What is the wishbone interface”?.
Wishbone is a flexible design methodology used for connecting different semiconductor IP cores. In the past, the IP core used non-standard interconnection schemes which made it difficult to be integrated with other IP cores. This required to build customized logic for each IP interface. The solution for this problem was simply to have a standard interconnection scheme which makes the integration of different IP cores easier and quicker. Wishbone used the “ master “ and “ slave“ architecture . The master and the slave are connected through an interface called “intercon”. The master starts the data transaction by sending the address and control signal to the slave, the slave then acts according to the received signals. The intercon is a medium that builds up of various logic and wires that helps the data get transferred between the slave and the master cores. The wishbone supports different types of interconnection such as point to point interface , shared bus interface and crossbar switch interface.
From the picture above it can be observed that the wishbone has common signals between the slave and the master like the reset and clock signals .The address signal (ADR_O) in the master is used to pass array signal that contains the address information to the slave . The data signal is also an array signal that passes the data from the master to the slave or vice versa.. The writing enable signal (WE_) is used to declare if the cycle is for writing or reading. The selection signal (SEL_) is used to indicate the place of the valid data in the data array. This was just a brief overview of the wishbone bus for more details about it and its signal kindly visit the following page.
As I stated above, my task was to wire and connect the different modules using the wishbone interface. According to the requirement, the top level module should have an instance of processor , switch (based on the number of the IO devices) and the instances of the modules that correspond to the user declared objects. As a beginning, Dr. Shawn asked me only to create a top level module that has a switch of 8 IO devices. The wiring process was not that difficult. In the instantiation of each module you should just give the same name of the port for the ports you want to wire and then define a wire variable that has that same name. This task was also easy with AUTO instantiation feature that is provided by the emacs (Refer to my previous entry for more info).
Some of the problems I faced was regarding the wiring for the port that has more than one pins like the data port , selection , and the address port . Dr. Shawn then told me that for the data port, the switch and IO device don’t need to have the same port size as the switch could be general and the IO device will be based on the user so then the connection will be starting from the least significant bits.For the address port, the master actually sends the address of the IO devices register that he wants to write to or read from. For instance: the gpio module has two register one for the data and the other one for the control, the IO has one bit address port whereas the switch has up to 32 bits address port so my concern was which pin should be connected to which pin, this was later declared by Dr. Shawn as the gpio pin would be always connected to the LSB pin of the switch address port.
The challenge now is to come up with a way to instantiate a switch module based on the number of devices the user declared in the C++ module.
We have two routes we can take in this matter, one is to build a big switch module that has many IOs devices interfaces or to have small switch blocks (1 to 4) then cascading those switches based on the requirement. The latest route is more efficient in term of chip design as it has faster processing as explained by Dr. Shawn.
So I’ll be working in that on the next week ..
(seems like I spoke too much this time.. heheh Wish me a good luck 😉 and thanks for reading!