A little bit of everything (Update March 2019)
This was rather a short week because of the Chinese New Year. Nonetheless, this week I was focusing on modifying AUTO_TEMPLATE for all different modules to generate a top level design. To start off, I was studying the CPU32 module taken from one of the projects and created an AUTO_TEMPLATE Read more
Creating a Wishbone RAM (Update March 2019)
Time was passing really fast and this was the eighth week of internship. In this week I was working on a Wishbone RAM. To start off, I had to understand the mechanism of a dual port RAM. The dual port RAM fundamentally consisted of an instruction port (read only) and Read more
A triangular timing diagram
In this week I was modifying the Wishbone switch so that it would gave correct signal outputs. To give an overview, the strobe signal from the previous wire must be passed to the next wire after one clock cycle, until it reached the I/O port. As a result, the I/O Read more
Connecting Wishbone switches
I continued to work on the Wishbone switch throughout the week. First of all, I added some additional signal ports to the Wishbone switch I created last week. Those additional signals were described as follows, based on the Wishbone specification. MASTER signals SEL_O: It denoted the location of valid data. Read more
A tale of a Wishbone switch
I was working on a Wishbone switch in this week. The switch would be able to pass data to either the downstream or the I/O device from the upstream. To design a Wishbone switch, it was crucial to understand all signals present in Wishbone. I would describe some Wishbone signals Read more
Diving right into Synthesis
In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer Read more
Wishbone Bus Interface
In the past week I managed to instantiate the modules based on the user declared objects. Each C++ declared object is corresponding to an instance module in verilog (you can refer to my previous blog entry for more information ). My task for this week was to connect and wire Read more
Completed GPIO using the Wishbone protocol
In my third week, I worked on designing a GPIO device that uses the wishbone protocol. This project was the same one i was working on last week. I was able to finish my part this week. My gpio basically consists of a direction register and a data register that Read more