In my second week, time was an issue. Therefore, I attempted to finish up more this week (my third week) so that I can cover the workload from week two. Generally, I am supposed to finish the opcodes by the end of this week. However, like 99% of the things with programming, it always ends up as an underestimation.
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For my second week, I couldn’t work as much as I imagined. After finishing the basic utilities and a general understanding of what I needed, I set off to write the opcodes. The opcodes require more time and effort because ultimately I would like to get it right the first time. However, that requires a general understanding of the aeMB processor.
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The journey of analysing AEMB is finally reaching a destination. In this post I will discuss AEMB’s interface with the data memory and with the accelerator bus. Moreover, I will explain the design of the execution unit and highlight some of it’s parts that I can’t comprehend yet. Finally I Read more…
Dissecting AEMB continues. In this post I will give an overview about the instruction set architecture (ISA) of the AEMB and its register file. Finally I’ll explain how AEMB communicates with the data memory and the accelerator bus. Since AEMB code is compiled using the Microblaze toolchain, the ISA of Read more…
Over the past weeks I’ve been exploring the architecture of microprocessors in general and AEMB’s in particular. I wish I can say I am done with dissecting AEMB but I ain’t. In this blog post I will give a quick overview about my project and give a functional description of Read more…
I’ve managed to completely remove the Icache from AEMB. Simulation and FPGA implementation were both a success. However, after the edits AEMB now runs slower because it has to fetch each and every one of it’s instructions through at least two Wishbone cycles. It’s worth mentioning that Before removing the Read more…
My new task is to remove the Icache module from AEMB. Basically Icache holds all instructions before execution by the core. Icache acquires the instructions from whatever is holding them externally and keeps them for processing. Icache controls the Instructions WB interface through the ich_hit signal. When the processor needs Read more…
The above blinking LEDs are not regular blinking LEDs. These LEDs are connected to the output of a GPIO. That GPIO is controlled by the AEMB2 microprocessor and the AEMB2 microprocessor is fetching it’s instructions from a 16K block RAM that has been loaded with data using the DATA2MEM software. Read more…
I’ve always dubbed the AEMB as the littlest processor that could, after the famous book with an engine. To figure out just how little it is? It occupies less than 20% of the real-estate in the second smallest Spartan6LX9 FPGA. Slice Logic Utilization: Number of Slice Registers: 866 out of Read more…
I’m a final year student from Multimedia University (MMU), currently pursuing Bachelor of Engineering (Honours) in Electronics. As for my first post in AESTE’s blog, I’m sharing my experiences on job application to AESTE, and the work progress thus far. The job application to AESTE involved two stages. The first stage Read more…