AEMB ISA, Registers, Memory
Dissecting AEMB continues. In this post I will give an overview about the instruction set architecture (ISA) of the AEMB and its register file. Finally I’ll explain how AEMB communicates with the data memory and the accelerator bus.
Since AEMB code is compiled using the Microblaze toolchain, the ISA of AEMB is pretty much the same ISA for the Microblaze EDK 6.3. Instructions are all 32 bits and they come in two types. Type A have two source registers, A & B, and a destination register, D. Type B has one source register, one destination register and a 16 bit immediate value. The Immediate value can be sign extended to 32 bits or the top 16 bits can be supplied from the immediate instruction to create a 32 bit value. Internally, AEMB groups the instructions into the following types; Arithmetic, Multiply, Barrel Shift, Return, Conditional and Unconditional Branches, Immediate, Load and Store and Get instructions. While Microblaze uses the GET instruction to access its Fast Simplex Link, FSL, The AEMB uses it to access its accelerator bus.
The Main difference between the AEMB register file and the Microblaze one is that AEMB uses 64 registers. Each 32 registers are used for one thread. The GPHA signal is used as the MSB of the address of the registers to determine which thread is currently active. The way the register file is coded in Verilog is that it instantiates 3 sets of 64×32 dual port RAMs. The synchronous write port shares exactly the same signals but the asynchronous read ports use the addresses of A, B or D registers. I am yet to discover whether this infers three sets of register or one set with some sort of multiple access for the the read port.
AEMB communicates with data memory and accelerator bus using the dwbif and xslif respectively. In these interfaces, the wishbone signals are defined and the data coming in from wishbone is latched on. AEMB accesses the data memory only on Load or Store instructions. Unlike with the instruction interface, the wishbone cycle and strobe signals in the data interface are not connected to each other. The Accelerator bus is accessed on Get and Put instructions.
To sum up, only the execution and branching aspects of the AEMB are left to be explored.