My new task is to remove the Icache module from AEMB.
Basically Icache holds all instructions before execution by the core. Icache acquires the instructions from whatever is holding them externally and keeps them for processing. Icache controls the Instructions WB interface through the ich_hit signal. When the processor needs an instruction that’s not available in Icache, the ich_hit signal is driven low which starts a wishbone transaction to fetch the instruction from the external source holding it.
Moreover, the Ich_fb signal which is exactly the ich_hit signal is used to determine the iena control signal generated by the Pipeline module.
To put it short, when ich_hit is low the wishbone interface is fetching instructions from the external source. On the other hand when the ich_hit is high the execution of instructions is enabled.
I’ve done a couple of tests trying to remove the Icache but none was successful though I learned valuable information from them.
Meanwhile, I’ve edited the test bench for AEMB allowing it to display transactions to the accelerator and to the GPIO address space along with the specific address used.