15- A new AEMB.
I’ve managed to completely remove the Icache from AEMB. Simulation and FPGA implementation were both a success.
However, after the edits AEMB now runs slower because it has to fetch each and every one of it’s instructions through at least two Wishbone cycles. It’s worth mentioning that Before removing the Icache at some points AEMB managed to execute instruction in one clock cycle. Thus I believe there is a big room for improvement even though it won’t be an easy task as it requires digging deeper into AEMB.
In this post I’ll explain the changes I’ve made to the AEMB.
First of all to make things simple I didn’t remove any of the internal AEMB signals except for ich_hit. All the signals are now generated by iwb_if imitating the behaviour of icache.
The ich_fb signal now works this way.
- It goes high once a wishbone transaction is acknowledged. Thus indicating that the instruction is ready for execution and allowing the address in preparation of fetching the next one.
- It goes low once the rADR which is exactly the iwb_adr_o changes. Once ich_fb goes low stb goes high on the next edge. Hence once the address changes a wishbone transaction takes place on the next edge to fetch the new instruction.
As for the ich_dat which is the internal signal carrying the instruction to be executed, I’ve used a register to hold each instruction once obtained from the RAM. The register imitates the RAM of icache in terms of read and write signals.
Meanwhile I’ve expanded the current SOC by adding the SHA1 accelerator to it and tomorrow We’ll test it using the SHA1 driver built by my colleague.
Last but not least I added to the simulator for AEMB the ability to display Accelerator bus transactions.