Partnership with Otak-Otak

We are happy to announce our parnership with Otak-Otak – The Internship Programme for Leaders. Quoting the official website: The Otak-Otak Program will be built around a first of its kind, unique talent development schedule consisting of leadership training and site visits. Our core mission is to connect top student leaders to Malaysian companies, select the 50 best interns to be placed in internships with our Corporate Partners, and to build meaningful internship experiences for both the Corporate Partner and Read more…

Why Engineers are Better-Off Joining Startups

There is an interesting article in TC recently, about how it is now an excellent time to join startups. Just to note that AESTE is HIRING NOW. Quoting the article: Today, most interesting technology is built directly for end users and it is a crucial skill for an engineer to understand quick iteration based on user feedback, however complex the technology. Increased technology and distribution leverage means that in the future, smaller teams are going to build higher impact things Read more…

Hardware-Assisted Synchronisation

An idea about hardware assisted synchronisation for the AEMB came about recently. The idea centered on the problem of how multiple threads would communicated between each other. The solution to this problem has always been synchronisation primitives. The AEMB already supports the atomic MSRSET/MSRCLR instructions, which can be used as a mutex primitive. This hardware mutex can be used to build additional synchronisation operations in software. However, this is an inefficient method for doing software synchronisation. Since the AEMB is Read more…

AEMB on Altera with uC/OS-II in China

Seems like there are three important pieces of news to report: that the AEMB has made in-roads into China; that the AEMB has been implemented on Altera hardware; and that the AEMB is capable of booting uC/OS-II. According to the information provided at a Chinese media website, a key Chinese university (Shandong University of Science and Technology) has successfully implemented an SoC system using the AEMB on an Altera platform and boots uC/OS-II. They published a paper on this earlier Read more…

Virtual Kernel

While everyone seems to be quite focused on high-end virtualisation, there is also room for virtualisation solutions at the low-end. One way of approaching this problem is by the use of a thin layer of virtualisation at the nano-kernel level. Instead of just abstracting hardware away, it is also possible to put in entirely virtual hardware devices for embedded applications. This allows things like I/O peripherals to be abstracted and run entirely as pure software only. The AENIX kernel will Read more…

Power Optimisation

Since the recent LLVM 2.7 release came with initial support for the Microblaze, it is now conceivable to add some features into the LLVM to enable power optimisation for the AEMB and other architectures. The reason that LLVM is chosen instead of GCC is purely subjective – a cleaner code base and the open license adopted. The idea of power optimisation lies behind the premise that power is a systems level problem – not a hardware one. While hardware is Read more…

New Multi-Threading Model

In order to streamline the new AEMB processor family, a new multi-threading model is being tested. In the new multi-threading model, each core will have at least the capability of running four threads either manually or automatically. For the AEMB1, the threads would need to be switched explicitly using special software break instructions while for the AEMB4, the context switching will happen automagically and the AEMB2 will be somewhere in between the two. As for the software, the AEMB1 will Read more…

In-Cache Execution Environment

The AEMB is designed with an FPGA target technology implementation. Since this is the case, it may be prudent to exploit certain FPGA capabilities that are not present on ASIC technologies. One such capability is the ability of an FPGA to pre-load the contents of block memories from an FPGA image. This ability is often used to create a read-only RAM block or ROM block. However, if the write-enable signal is enabled this ability can be used to pre-load the Read more…

Conjoining Resources

Since increased concurrency seems like the way to go for computing, I am interested in increasing the concurrency of the AEMB from 2 to 4 hardware threads. This can be done through a dual-core set up. However, I plan to make my dual-core AEMB special by sharing resources between them so that it doesn't actually cost twice the amount of chip resource to implement two cores. So, it is more like having the power of two cores at the cost Read more…