Engineering Elegance

ASH1 has 2 output ports and 1 input port whose specifications are like the following: Input Port 0 (iport0) An 8-bit input port with 4 schemes of encoding (table 1): Encoding Scheme Description 00 Non-Return-to-Zero-Level  (NRZL) 01 Non-Return-to-Zero-Inverted (NRZI) 10 Differential Encoding with Non-Return-to-Zero-Inverted (NRZI) 11 (same as 00) – can be modified in the future For NRZL, ASH1 will push/load the status of iport on the stack directly with no specific form of signal shaping. For NRZI, ASH1 will Read more…

  ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals: Interfacing with Signal Width Direction/ Type (with respect to ASH1) Master CPU clk 1 i reset 1 i strb_wb 1 i we_wb 1 i ack_wb 1 o data_i_wb 8 i data_o_wb 8 o addr_wb 8 i int_ack 1 i int0 1 i int1 1 i int2 1 Read more…

One of ASH1 features is that it can perform – what we can call – software-controlled CRC calculation. As we know CRC incorporates bit shifting, xoring and in sometimes inversion. We decided to have a unit in ASH1 that is dedicated to all these operations. For instance, we want to calculate CRC for a data byte prior to its transmission, we would simply push the byte on the stack, signal the CRC unit to start the calculation and then -without Read more…

It has been a while since my last blog … I was busy with my exams and university issues  for about a month. So, here we come again to talk about ash1. Since I have started working on ash1, I was anxiously waiting for the day where I can write a piece of code and test it out on an FPGA device and this is what happened ! On 20th of August, 2011, ash1 executed its first program that I Read more…