I have mentioned many times that ASH1 should be as small and as fast as possible… The current version of ASH1 is able to perform USB functions pretty good ( more specifically 1.5 Mbps USB operations) and other simple I/O operations.
However, getting myself into Ethernet and trying to integrate it into ASH1 lets me see potential chances for improvement of ASH1. For example:
- Although, PUSH & POP are frequent operations of a stack-based processor, I designed ASH1 to do most of the job with least number of PUSH/POPs, which adds up some complexity on FLAG/STACK units of ASH1.
- Instruction Width & Stack Width: Currently ASH1’s instructions are 14-bit wide instructions, which limits the amount of data to be deal with. Having 32-bit instructions would increase the chances of implementing absolute branching/jumping over a relative one. Also having a 16-bit wide stack would reduce the degree of complexity of the design when interfacing the stack with other unit of ASH1.
- ASH1/Master CPU Data Center: ASH1 is communicating with the master CPU via the wishbone bus through 3 data centers (storage) that are Tx, Rx buffers and a register file which complicates the wishbone interface and adds up additional things to care about. Ethernet operations made me think of excluding the the buffers and use the register file (RAM) only. The reason behind that was the fact that some data might need to be re-transmitted again which will be difficult when we’re dealing with buffers ( need to be re-filled again prior to re-transmission).
- CRC unit : CRC unit in ASH1 was implemented as a state machine that’s controlled by an instruction but now I am thinking of implementing a parallel architecture for CRC which makes it faster and smaller.