Tagged: iop

ASH1 Assembler

During the last week, I worked on developing an assembler for ASH1! I have always wondered about the assemblers & compilers design… with AESTE, I had the chance to explore this field. ASH1 assembler...

CRC Operations: A follow-up

Cyclic Redundancy Checksums generation and checking were among the challenging things in implementing ASH1. Looking for the accurate way to calculate/check CRCs took me a lot of time as it was confusing in terms...

Ethernet Operations: Random Generator

Back-off is an important feature of the Ethernet MAC protocol. After a collision is detected through the MII/RMII interface, ASH1 should stop transmitting (there are more specific details about when exactly to stop transmission)...

ASH1: Input and Output Ports

ASH1 has 2 output ports and 1 input port whose specifications are like the following: Input Port 0 (iport0) An 8-bit input port with 4 schemes of encoding (table 1): Encoding Scheme Description 00...

ASH1 : Life Cycle

ASH1 is growing and the design is being modified continuously to allow for further flexibility and capability in performing I/O operations. However, these modifications won’t be drastic. ASH1 core is there ! So in...

ASH1: Communication Protocol

  ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals: Interfacing...

ASH1: An Overview

As I have mentioned in the previous post, this and the coming posts would describe ASH1 architecture and special features. Below is the block diagram of ASH1.   It consists of a data stack,...