Engineering Elegance

Productive Week

This week’s work was very productive in the way that I was able to complete the design flow from synthesis to bitstream generation (excluding bram content replacement) for all 6 fpga types: Xilinx 7 series, Cyclone V, Cyclone IV, Lattice ECP5, Lattice ICE40, and Spartan 6 (which implements the ISE flow). All flows are able to retrieve a Verilog file, a constraints file for determining the pinouts of the design, and additional arguments to generate a single bit file ready Read more

By Myeong Jin, ago

Good Progress

At the end of this week, I was able to speak with my supervisor to discuss my progress, mistakes, and next steps. During this discussion, we talked about the importance of representing a product in an understandable and simple manner in engineering, and I thought this was noteworthy. As this is my first time being in a working environment, I feel like I am starting to learn what it means to be in the producer’s shoes instead of the consumer, Read more

By Myeong Jin, ago

Changing the K3 Code

This week’s work was focused on writing the code to operate the design flow tools for the Xilinx 7 series, Intel Cyclone V, and Lattice ECP5. I had to gather all the tools I have found during the first few weeks of internship and integrated it into the K3rangka code. One main challenge to writing the code was to become familiar with the external library, Poco. My supervisor told me to operate the tools using only functions of Poco without Read more

By Myeong Jin, ago

Starting to Code

I have finally begun making changes to the K3rangka code, trying to isolate the implementations of running yosys, nextpnr, and other tools into separate classes. Previously, the implementation was within the resource file that handles the HTTP requests. The implementation handled different type of FPGAs through if statements, which was possible for the ice40 and ecp5 due to their similarities in the open-source design flow. However, the implementation would be very different for the Xilinx 7 series and the Cyclone Read more

By Myeong Jin, ago

Almost There

My search for the tools in Vivado and Quartus has come to an end. After three days of unsuccessful attempts to track down the processes while running Vivado and find the tools for each part of the design flow, I have given up and decided to resort to tcl commands which is well documented and also suggested on the yosys wiki page. The Vivado processes had dependencies such as libraries to be preloaded or variables of paths to be specified, Read more

By Myeong Jin, ago

Searching for the Right Tools

This week, I was focused on finding tools for FPGA boards besides the Ice40 (Lattice ECP5, Xilinx Series 7, and Intel Cyclone V). My starting point was my supervisor’s suggestion to look at project Trellis, X-Ray, and Mistral for each of the boards respectively. Out of the three projects, project Trellis seemed to have the most progress as it was able to support a full design flow from Yosys to nextpnr to bitstream generation using a tool named ‘ecppack’. However, Read more

By Myeong Jin, ago
Photo by Tim Gouw on Unsplash

Getting Started

During my second week of internship, I encountered two unexpected surprises concerned with the project I was given. My project was the continuation of what another intern, Jun Wen, was working on. It was the development of a web application that would simplify the programming of different models of FPGAs. My first surprise was that I was going to work with FPGAs instead of microprocessors (which I was expecting). This meant that I had to study at least the very Read more

By Myeong Jin, ago

Final Week

This will be my last week of internship in Aeste. I finished up my work on code refactoring. As this will be the last blog entry from me, I would like to write on the learnings and reflections throughout this internship.  I have obtained various technical skills, namely  Git version control Web development programming language Javascript Web development framework VueJs With no previous experience in any of these skills, I am happy to say that I am able to develop Read more

By Kai Jun, ago
Photo by Fabian Grohs on Unsplash

multipart/form-data

I mainly focused on generating a multipart message this week. I was using curl to send a multipart formpost previously. For example, curl -kv -F ‘lang=vlog’ -F ‘[email protected]’ http://127.0.0.4:8080/api/v19/workspace.elaborate was used to transfer data to a server. The request body was shown below. (Note: A boundary was a string of random numbers.) –MIME_boundary_2CA6E12165908974 Content-Disposition: form-data; name=”lang” vlog –MIME_boundary_2CA6E12165908974 Content-Disposition: form-data; name=”…”; filename=”source.v” Content-Type: text/plain (contents of the file) –MIME_boundary_2CA6E12165908974– Instead of using curl to transfer a multipart message, I had Read more

By Jun Wen, ago

Slight Obstacles

I spent almost the whole week on code refactoring. It is a process which takes up quite a lot of time as much thinking is needed to optimize the code for easier maintenance in the future. My progress on refactoring was satisfactory, except for a small part where I am slightly stuck. In VueJs, v-model is a feature for two way data binding. This means that a variable is binded to an event listener. A change in input will generate Read more

By Kai Jun, ago